How full should the core be? Too empty, and the chip is larger than it needs to be and its wires are long. Too full, and the placer and router run out of room. The best way to understand the trade-off is to measure it. This article runs the same design, the 16x16 multiplier, at core utilizations from 20 % to 75 % and compares die size, wire length, layer usage and timing, then shows what happens when the target is too high or impossible.
8 min read | Intermediate
What You'll Learn
- Measure how utilization changes die size, wire length and timing
- Explain why very low and very high utilization both hurt
- Recognize the signs of a floorplan that is too full
- Run a utilization sweep in the lab
The Sweep
The multiplier has 9,668 um2 of cells from synthesis. Each run sizes the core for a different utilization in the lab's panel; everything else is identical (10 ns clock, sky130 hd, typical corner):
| Utilization | Die (um) | Final utilization | Signal wire | met3 + met4 wire | Worst slack |
|---|---|---|---|---|---|
| 20 % | 239.9 | 23 % | 33.5 mm | 3.4 mm | +0.16 ns |
| 30 % | 199.5 | 33 % | 29.8 mm | 4.2 mm | +0.34 ns |
| 40 % | 175.5 | 44 % | 27.9 mm | 3.3 mm | +0.13 ns |
| 50 % | 159.1 | 55 % | 26.3 mm | 4.0 mm | +0.34 ns |
| 60 % | 146.9 | 65 % | 26.0 mm | 4.6 mm | -0.37 ns |
| 70 % | 137.5 | 76 % | 27.1 mm | 6.0 mm | -0.09 ns |
| 75 % | 133.5 | 81 % | 28.4 mm | 6.3 mm | -0.43 ns |
All seven runs route without violations and pass DRC and LVS.
Reading the Results
Low utilization: long wires
At 20 % the die is 3.2 times the area of the 75 % die. The cells are spread out, and the wires are 33.5 mm in total, 29 % more than at 50 %. Timing still passes at 10 ns, but with less slack than at 30 % or 50 %. A half-empty core is not a safe choice: it costs area, and its longer wires cost power and speed.
The sweet spot
Wire length falls steadily up to 50-60 %, where it reaches 26.0 mm. In this range the cells are close together and there is still enough room for routing on met1 and met2. The slack does not follow the wire length neatly, because each run has its own placement and repair results: +0.34 ns at 50 %, but only +0.13 ns at 40 %.
High utilization: crowding
From 60 % on, the routed design misses the 10 ns clock, although the total wire is as short as at 50 %. The worst path at 60 % is the same chain of 31 cells as at 50 %, with the same cells, yet it is 0.69 ns slower: several of its nets carry much more wire capacitance, for example 17.5 fF instead of 7.3 fF on one nand4_1 output, because in the crowded core the router had to detour them. The repair step before routing saw only one failing endpoint at 60 %, because it judged the wires from the placement, where they were still short. Total wire length says little about the few nets that matter. A second repair after global routing, which sees the detours, fixes this: with the lab's PRO option for it, the same netlist met 10 ns with +0.63 ns at 60 % and +0.44 ns at 75 %.
At 70 and 75 % the total wire length rises again, to 28.4 mm, and more of it goes to met3 and met4, 6.3 mm against 3 to 4 mm below 60 %: the lower layers are crowded, so the router takes detours up and around. The design still routes, but the margin is gone. A larger or more connected design would hit routing congestion and DRC violations sooner; Global Routing and Congestion shows how to see it coming.
Quick Check
Q: The final utilization is always a few percent above the target. Why?
Show Answer
The core is sized for the synthesized cells only. Tap cells, clock buffers and the cells upsized or inserted by timing repair are added later, and they take area in the same core.
When the Target Is Impossible
The lab's panel accepts up to 75 %. Beyond that, with a die area set directly (a PRO option), the problems grow quickly. At 84 % (a 129.93 um die), global routing failed with the flow's normal routing reserve and passed only on its retry with a smaller one, and detailed routing did not finish within the 30 minutes a PRO job may run. At 95 %, the flow stops right at the start of global placement:
[ERROR GPL-0301] Utilization 106.180 % exceeds 100%.
The placer adds the tap cells and a pin-density allowance (extra area around cells with many pins) to the cell area, which pushes the 95 % core past 100 %. There is no legal solution, and the tool says so immediately. Real designs fail much earlier, not with an error but with routing congestion that cannot be resolved.
Quick Check
Q: Why does a design with many small, highly connected cells reach its practical limit at a lower utilization than one with large cells?
Show Answer
Routing demand grows with the number of pins and nets, not with cell area. Many small cells pack many pins into a small area, so the wires run out of tracks before the rows run out of sites.
Running It in ChipVerify Lab
The lab's panel sizes the floorplan for the utilization you enter, up to 75 %, so the whole sweep above can be run in the lab. Each run took about 3 to 5 minutes; the 75 % run came close to the 5-minute limit of the free tier. With PRO, set the die area instead to go further: the lab keeps a 10 um margin inside the die, so 0 0 129.93 129.93 gives the 84 % core described above, and 0 0 120.9 120.9 the 95 % one.
Common Mistakes
Mistake #1: Starting with a very low utilization "to be safe"
As the 20 % run shows, an empty core makes the die large and the wires long. Start around 50 % for logic and adjust from measurements.
Mistake #2: Judging by placement alone
A design can place at 85 % and still fail routing. Look at congestion after global routing and at the final DRC count before deciding a utilization works.
Practice Exercise
Challenge: Run the Left Half of the Sweep
Run the multiplier at 20 %, 30 % and 40 % utilization. For each run note the die size, the worst slack and, from the CTS section, the number of clock buffers. Does the clock tree change with the die size?
Hint
CTS sizes the tree mainly from the number of flip-flops it must reach, 64 here.
Solution
Die sizes 239.9, 199.5 and 175.5 um, slack +0.16, +0.34 and +0.13 ns. The clock tree is the same size in all three runs: 9 buffers, 2 buffers deep to every flip-flop, because it is built for the same 64 sinks. What changes is the wire: the log reports an average sink wire length of 116 um at 20 %, 119 um at 30 % and 135 um at 40 %. Where the flip-flops happen to cluster matters as much as the die size.
Open the ready-made example in the lab, synthesize it and run Place and Route.
Summary
- Low utilization costs area and wire length: at 20 % the multiplier needed 29 % more wire than at 50 %.
- Wire length was lowest around 50-60 %.
- From 60 % the routed design missed 10 ns: detours on a few critical nets, which the pre-route repair did not see; a repair after global routing closed it. At 84 % routing did not finish in 30 minutes; at 95 % placement failed with GPL-0301.
- Final utilization is always above the target because of taps, clock buffers and timing repair.