Physical Design Checklist

This checklist follows a Place and Route run from start to finish and lists, for each step, what to look for in the log and the report: the message that tells you the step worked, the number to check, and the warning that means trouble. It is the practical companion to the Physical Sign-Off Checklist, which covers the final checks. Use it on every lab run, and the habits carry over to any OpenROAD-based flow.

8 min read | Intermediate

What You'll Learn

• Check each step of a Place and Route run from its log messages
• Know the normal numbers for a small design and the warnings that matter
• Recognize the setting and constraint traps found in this tutorial
• Decide when a run is ready for sign-off

Before the Run

• Netlist without constants on cell pins. A synthesized netlist with 1'b1 or 1'b0 on a cell input needs tie cells. Without them, detailed routing stops with DRT-0305 Net one_ of signal type POWER is not routable. Check the synthesis output, or see Project: Place and Route a UART Transmitter for how this shows up. The lab's synthesis maps constants to tie cells itself.
• Constraints. A clock on the right port, and input and output delays for the I/O paths. Without them, I/O paths are never timed.
• Settings recorded. Utilization, clock period, library and corner, and any script changes: the same netlist gives different results with different settings.

Floorplan

[INFO IFP-0001] Added 56 rows of 337 site unithd.
[INFO TAP-0005] Inserted 319 tapcells.

• Rows and sites give the core size: rows x 2.72 um by sites x 0.46 um in sky130 hd.
• The tap cell count follows from the rows and the tap distance.
• Pins on the intended edges and layers in the layout viewer.

Details: Floorplan Checks.

Power Grid

• Rails on every row and straps on the upper layers. A grid with met1 rails only shows PSM-0038 unconnected-shape warnings and fails the IR drop connectivity check.
• After routing, check_power_grid per supply should report PSM-0040 All shapes on net VDD are connected.

Details: Building a PDN in OpenROAD.

Placement

[INFO GPL-0023] Placement target density:       0.5000
[INFO GPL-1004] Minimum Feasible Density        0.4500 (cell_area / free_area)

• Target density a little above the minimum feasible density. Far above it, cells cluster and leave empty space; the multiplier at 0.95 in a 78 % core could not be routed on two layers.
• Legalization: the legalized HPWL should be close to the global placement HPWL; a large increase means overfull regions.
• Timing-driven placement needs a clock. GPL-0102 Timing-driven: no slacks found means it ran without timing.
• check_placement passes with no overlaps.

Clock Tree

[INFO CTS-0010]  Clock net "clk" has 97 sinks.
[INFO CTS-0018]     Created 9 clock buffers.

• The sink count equals the number of flip-flops (and clock gates).
• Skew and latency in the CTS report are within budget.
• Hold checked with the propagated clock; hold repair if needed.

Details: CTS in OpenROAD and Skew, Useful Skew and Hold.

Timing Repair

• The repair table: WNS and violating endpoints before and after, and the area increase.
• RSZ-0062 Unable to repair all setup violations means the remaining paths need a design change or a longer clock.
• Slew and capacitance violations cleared; in sky130 the fanout limit has no effect.

Global Routing

[INFO GRT-0096] Final congestion report:
... Total   28403   3945   13.89%   0 / 0 / 0

• Zero overflow in the final report.
• Few or no GRT-0101 extra iterations; dozens mean the design is at the limit.
• The capacity reserve, shown as derated resources in the routing resources table (GRT-0053): zero overflow with no reserve proves little.

Details: Global Routing and Congestion and Debugging Congestion.

Detailed Routing

[INFO DRT-0199]   Number of violations = 427.
...
[INFO DRT-0199]   Number of violations = 0.

• The violation count falls pass by pass to zero. A count that stalls, or jumps back up repeatedly, is a placement or congestion problem.
• Run time: a few minutes for the tutorial's designs. Tens of minutes on the same design means an overpacked placement.
• DRT-0305 ... not routable means a constant net without a tie cell.

Antenna and Fill

[INFO ANT-0002] Found 0 net violations.
[INFO DPL-0001] Placed 2442 filler instances.

• Zero antenna violations on the final routes.
• Fillers placed in every gap.

Timing After Routing

• Worst setup and hold slack, and the critical path, from extracted parasitics. The lab's report shows the estimate before extraction too; only the extracted numbers count.
• The path makes sense: launch and capture clocks with similar latency, no single stage with an extreme slew or load.
• The design meets the target at the corners it must work at, not only at typical.

Physical Checks

• Stream-out without "Invalid via name" or missing-cell warnings.
• DRC on the GDSII: zero violations.
• LVS on the GDSII: "Circuits match uniquely".

Details: GDSII Out and Tapeout, DRC and LVS.

Ten Rules From This Tutorial

1. Read the warnings, not only the result line.
2. Compare runs only with the same settings, and record the settings.
3. Set constraints before the steps that use them.
4. Keep the placement density close to the utilization.
5. Judge a global route by its overflow and its reserve together.
6. Watch the trend of detailed routing violations, not the first count.
7. Trust extracted parasitics, not estimates, for final timing.
8. Check setup at the slow corner and hold at the fast corner.
9. Run DRC and LVS on the streamed GDSII; they catch different errors.
10. When a path has too many logic stages, fix the design, not the layout.

Running It in ChipVerify Lab

Run Place and Route on any of the tutorial's examples and go through the list with the OpenROAD log section of the report open. The message IDs above appear in the same form in the lab's log.

Common Mistakes