Design for Manufacturing and Yield

Design for manufacturing (DFM) is the set of layout practices that make a chip more likely to work after fabrication, beyond simply passing the design rules. DRC rules are minimums: a layout that sits at the minimum everywhere is legal but fragile, because random defects and process variation hit tight spacings and single vias first. Yield, the share of manufactured dies that work, depends on how much of the layout is exposed to those effects. This article explains the main yield mechanisms, how layout choices change them, and what the routed 16x16 multiplier looks like from that point of view.

7 min read | Intermediate

What You'll Learn

• Explain random and systematic yield loss
• Describe critical area and how spacing and width change it
• List the common DFM fixes: redundant vias, wire spreading, fill and recommended rules
• Estimate die yield from area and defect density

Why a DRC-Clean Layout Can Fail

Two kinds of problems reduce yield:

• Random defects. Particles land on the wafer during processing. A particle between two wires can short them; a particle on a wire can cut it. The probability depends on how much of the layout is vulnerable.
• Systematic effects. Some patterns print or polish poorly every time: dense line ends, isolated narrow wires, areas of very different metal density, single vias in stressed locations. They fail by the shape, not by chance.

DRC catches neither. Its rules are the minimum the process supports, and a layout that meets every minimum can still be much more exposed to defects than one with a little margin.

Critical Area

For a defect of a given size, the critical area is the part of the layout where the centre of that defect would cause a failure. For shorts, it is the area between wires closer than the defect size; for opens, the area of wires narrower than the defect. Wires at minimum spacing create critical area for small, frequent defects; the same wires spread apart only fail for larger, rarer ones.

Critical area analysis integrates this over the defect size distribution measured by the foundry and gives the expected number of faults per die. Lowering it means spreading wires where there is room and widening wires where they are long and isolated.

Common DFM Fixes

• Redundant vias. A single via cut can fail open or have high resistance. Replacing it with two cuts where space allows makes the connection survive one bad cut. Foundries often list a double-via rate as a recommendation.
• Wire spreading and widening. After routing, move wires off minimum spacing into free tracks and widen long isolated wires, lowering critical area for shorts and opens.
• Metal fill. Even density for polishing, as in Fillers, Metal Fill and Density Rules, avoids dishing and thickness variation that change resistance and can open thin wires.
• Recommended rules. Besides the minimum rules, foundries publish recommended values: larger enclosures, wider spacing at line ends, preferred via configurations. Meeting them where possible costs little and improves yield.
• Lithography checks. Simulating how the masks print finds hotspots, patterns that pass DRC but print badly, which are then reshaped.
• Antenna fixes, as in The Antenna Effect, prevent gate damage during processing, another manufacturing-driven rule.

The Multiplier from a DFM View

The routed multiplier passed DRC and LVS, but it was routed for function and timing, not for yield:

• Every signal via is a single cut: 4,339 li1-to-met1, 4,069 met1-to-met2, 98 met2-to-met3 and 4 met3-to-met4 vias, all of the predefined single-cut types. A redundant via pass would add a second cut to as many of them as space allows.
• The wiring is concentrated on two layers: 13,060 um of signal wire on met1 and 14,383 um on met2, against 748 um on met3 and 111 um on met4. The upper layers have free tracks; spreading wires into them, or moving long routes up, would lower critical area on the crowded lower layers.
• Metal density is low and uneven without fill, and still below the 35 % window minimum after fill, as measured in Antenna, ERC and Density Checks.

None of these is a rule violation, and for a small block in a mature 130 nm process their effect on yield is modest. In large chips and advanced nodes, the same habits decide whether a design yields well.

Estimating Yield

A simple model treats defects as randomly distributed with an average density D0 per unit area. The probability that a die of critical area A has no defect is then the Poisson yield:

Y = exp(-A x D0)

More realistic models account for defects clustering on the wafer, which gives somewhat higher yields for the same average density, but the trend is the same: yield falls exponentially with area. That is why large dies are expensive, why designs with spare elements, such as memories with redundant rows, can repair defects, and why DFM fixes that reduce the effective critical area pay off most on large chips.

Running It in ChipVerify Lab

Run Place and Route on the multiplier and look at the routed layout: the single-cut vias at the cell pins, the dense met1 and met2 in the middle and the nearly empty upper layers. At the time of writing the lab's flow does not insert redundant vias or spread wires; metal fill is a PRO option, described in Filler Cells, Metal Fill and Density Rules, and the DRC deck checks the minimum rules only.

Common Mistakes