Multi-Vt design uses standard cells built with transistors of different threshold voltages: low-Vt cells that are fast but leak, and high-Vt cells that are slower but leak far less. The flow uses slow, low-leakage cells everywhere it can and fast cells only on critical paths. This article explains where leakage comes from, how Vt swapping trades it against speed, what sky130 offers, and how strongly leakage depends on temperature, measured on the routed 16x16 multiplier and in the sky130 libraries.
7 min read | Intermediate
What You'll Learn
- Explain the sources of leakage and why it depends on threshold voltage and temperature
- Describe how multi-Vt optimization swaps cells
- Read leakage from a power report and from Liberty data
- Choose the corner at which leakage must be checked
Where Leakage Comes From
A transistor that is off still conducts a little current:
- Subthreshold leakage flows from drain to source when the gate is below the threshold voltage. It falls exponentially with the threshold voltage and rises steeply with temperature. It is usually the largest part.
- Gate leakage tunnels through the thin gate oxide.
- Junction leakage flows through the reverse-biased junctions of drain and source.
Leakage flows as long as the supply is on, whether the circuit switches or not. For a chip that is idle most of the time, it can be most of the energy it uses.
Multi-Vt Cells and Vt Swapping
A foundry offers transistors with different threshold voltages by changing the implants. A multi-Vt library contains each cell in several versions with the same footprint and pins, for example low-Vt (LVT), standard-Vt (SVT) and high-Vt (HVT). Because the footprints match, one version can replace another without moving anything:
- Synthesis or the first placement uses mostly HVT cells, for low leakage.
- Timing repair swaps cells on critical paths to SVT or LVT, buying speed where it is needed.
- Late in the flow, power recovery swaps cells on paths with plenty of slack back to HVT.
OpenROAD's repair_timing includes Vt swapping among its moves and reports it in its summary. On the multiplier in Fixing Setup in Layout, the summary read Resized 91 instances: 91 up, 0 up match, 0 down, 0 VT: no Vt swaps, because the sky130 hd library has one threshold flavour per cell.
The transistors inside the hd cells show which one. LVS extraction of the multiplier, in Layout Versus Schematic, found 5,567 transistors of type nfet_01v8 and 5,561 of type pfet_01v8_hvt: the hd library uses the high-Vt PMOS throughout. In sky130 the choice of library (hd, hs, ms or ls) is the main lever between density, speed and leakage, rather than Vt swapping within one library.
Quick Check
Q: Why must the Vt versions of a cell have the same footprint and pin positions?
Show Answer
So that a swap late in the flow, after placement and routing, does not move anything: the new cell fits in the same sites and its pins are where the routes already land. A swap that changed the footprint would need legalization and rerouting, which could undo the timing gain.
Leakage in the Multiplier
The routed multiplier at a 10 ns clock was analysed with the hd library at three corners, using the same layout and extracted parasitics:
| Corner | Total power | Leakage power | Leakage share |
|---|---|---|---|
| tt, 1.80 V, 25 °C | 3.83 mW | 3.79 nW | 0.0001 % |
| ff, 1.95 V, -40 °C | 4.41 mW | 8.20 nW | 0.0002 % |
| ss, 1.60 V, 100 °C | 3.03 mW | 5.34 uW | 0.18 % |
At 100 °C the leakage is about 1,400 times its value at 25 °C, even though the ss corner has slow transistors, which on their own leak less. Temperature dominates. The fast corner, with fast transistors at -40 °C, leaks only twice as much as typical.
The same pattern appears cell by cell in the Liberty files:
| Cell | Area | tt, 25 °C | ff, -40 °C | ss, 100 °C |
|---|---|---|---|---|
inv_1 | 3.75 um2 | 5.3 pW | 3.1 pW | 4.03 nW |
nand2_1 | 3.75 um2 | 2.1 pW | 3.1 pW | 2.27 nW |
dfxtp_1 | 20.0 um2 | 8.4 pW | 14.5 pW | 14.65 nW |
For this small design at 130 nm, leakage is negligible against the 3 to 4 mW of dynamic power at every corner. In advanced processes, with much lower threshold voltages and billions of transistors, leakage can be a large share of a chip's power, and multi-Vt optimization is a standard part of every flow.
Checking Leakage at the Right Corner
Leakage sign-off uses the corner where it is highest: fast transistors at high temperature and high voltage. In the sky130 hd corners available here, the hot slow corner (ss, 100 °C) leaks most, because no corner combines fast silicon with high temperature. A product with a leakage limit, such as a battery-powered device with a standby budget, needs a library characterized at its own worst case.
Quick Check
Q: The ff corner has the fastest transistors, yet the ss corner leaks 650 times more. Why?
Show Answer
The ss corner is at 100 °C, the ff corner at -40 °C. Subthreshold leakage rises steeply with temperature, far more than it changes between process corners, so the hot corner leaks most even with slower transistors.
Reducing Leakage
- High-Vt cells wherever timing allows, with low-Vt cells only on critical paths.
- Power gating: switch off idle blocks completely, as described in Power Gating: Switches, Retention and Rush Current.
- Lower supply voltage for blocks that do not need full speed.
- Body biasing: raising the threshold voltage of idle blocks by biasing their wells, where the process supports it.
- Thermal design: a cooler chip leaks less, which is one reason leakage and temperature feed each other.
Running It in ChipVerify Lab
Run Place and Route on the multiplier and open the Power section of the report: it splits the power into internal, switching and leakage parts. Then choose a different corner for synthesis and Place and Route and compare the leakage column. Note that the lab synthesizes and places the design again for the chosen corner, so the layouts differ slightly; the table above used one layout analysed at three corners.
Common Mistakes
Mistake #1: Checking leakage at the typical corner
At 25 °C the multiplier leaked 3.79 nW; at 100 °C 5.34 uW. Standby budgets must be checked hot.
Mistake #2: Using low-Vt cells everywhere for speed
Low-Vt cells close timing quickly but multiply leakage. Use them only on paths that need them and recover power elsewhere.
Mistake #3: Ignoring leakage in an idle design
A chip that sleeps most of the time spends much of its energy on leakage. Power gating and high-Vt cells matter more there than in a chip that always runs.
Practice Exercise
Challenge: A Standby Budget
A battery-powered sensor keeps 64 flip-flops and 400 other cells powered in standby. Use the dfxtp_1 leakage for the flip-flops and the inv_1 leakage for the other cells. What is the standby leakage at 25 °C and at 100 °C? The budget is 1 uW.
Hint
Multiply the per-cell leakage by the cell count at each temperature.
Solution
At 25 °C: 64 x 8.4 pW + 400 x 5.3 pW = 0.54 + 2.12 = 2.7 nW, far below 1 uW. At 100 °C: 64 x 14.65 nW + 400 x 4.03 nW = 0.94 + 1.61 = 2.55 uW, over the budget. The design passes at room temperature and fails hot; the fix would be power-gating the logic that need not stay on, or a lower-leakage library.
Open the ready-made example in the lab, synthesize it and run Place and Route.
Summary
- Leakage comes mainly from subthreshold current, which falls exponentially with threshold voltage and rises steeply with temperature.
- Multi-Vt libraries offer footprint-compatible cells with different thresholds; flows use high-Vt cells by default and swap to low-Vt on critical paths.
- sky130 hd has one Vt (its PMOS is the high-Vt device), so repair reported 0 Vt swaps.
- The multiplier's leakage was 3.79 nW at 25 °C and 5.34 uW at 100 °C, about 1,400 times more; leakage must be checked hot.