Overview of Digital Design Flow

Introduction

Welcome to the foundational module of our RTL-to-Synthesis journey! If you've written some Verilog or VHDL code and simulated basic circuits, you're ready to take the next step: understanding how your hardware descriptions transform into real silicon. This module bridges the gap between writing code and creating actual chips, introducing you to the complete digital design flow and the tools that make it all possible.

The RTL-to-Silicon Pipeline: Your Design's Journey

Think of digital design as a translation process. You start by describing what you want your circuit to do in a hardware description language (HDL), and through several sophisticated steps, that description becomes a physical layout ready for fabrication. Let's walk through each stage of this transformation.

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Stage 1: RTL (Register Transfer Level)

RTL is where your design journey begins. When you write Verilog or VHDL code, you're describing how data moves between registers and how it's processed along the way. At this level, you're thinking in terms of always blocks, if-else statements, and data assignments—abstractions that describe behavior rather than specific gates or transistors.

For example, when you write assign sum = a + b;, you're describing an addition operation at the register transfer level. You're not specifying whether this should be a ripple-carry adder, a carry-lookahead adder, or any particular implementation—just that two values need to be added.

Stage 2: Simulation – Testing Before Building

Before moving forward, you need confidence that your RTL actually does what you intend. This is where simulation comes in. Using tools like Icarus Verilog, Verilator, or commercial simulators like ModelSim, you can execute your HDL code with test inputs and observe the outputs.

Simulation operates at the functional level. Your testbench applies stimulus signals, and the simulator calculates how your design responds cycle by cycle. This is your opportunity to catch logical errors, timing issues, and corner cases before investing time and resources into synthesis. Think of it as proofreading your design before publishing.

The key outputs from simulation are waveforms—visual representations of how signals change over time—and log files that can verify expected behaviors. A well-simulated design gives you confidence to move forward, though simulation alone cannot catch every issue that might arise in physical hardware.

Stage 3: Synthesis – From Behavior to Structure

Here's where the magic happens. Synthesis tools take your behavioral RTL description and transform it into a gate-level netlist—a structural representation using actual logic gates (AND, OR, NOT, flip-flops, etc.) from a target technology library.

The synthesis process involves several sub-steps:

• Elaboration: The tool first parses your RTL and builds an internal representation, resolving hierarchies and parameters.
• Optimization: The synthesizer applies various transformations to optimize your design. It might restructure logic to reduce area, improve speed, or lower power consumption. That a + b operation? The tool decides the best adder architecture based on your constraints.
• Technology Mapping: This is where synthesis becomes technology-specific. The optimized logic gets mapped to actual standard cells from your Process Design Kit (PDK). A PDK contains the physical implementations of basic gates and flip-flops available in a particular fabrication process.
• Constraint-Driven: Modern synthesis is heavily constraint-driven. You tell the tool your clock frequency requirements, area budgets, and power targets, and it attempts to meet those goals while mapping your design to gates.

The output is a gate-level netlist, typically in Verilog format, where every element corresponds to an actual standard cell that can be physically implemented.

Stage 4: Timing Analysis – Will It Actually Work?

Having a netlist isn't enough. You need to verify that your design will function correctly at the intended clock frequency when built in silicon. This is where Static Timing Analysis (STA) comes in.

STA examines all paths through your circuit—every route that signals can take from input pins through combinational logic to flip-flops and outputs. It calculates propagation delays considering:

• Gate delays (how long each logic cell takes to produce an output)
• Wire delays (how long signals take to travel through interconnect)
• Clock distribution delays (skew and jitter in your clock network)

The tool checks for setup time violations (data arriving too late before the clock edge) and hold time violations (data changing too soon after the clock edge). These violations indicate that your circuit won't work reliably at the target frequency.

If timing violations exist, you have several options: adjust synthesis constraints, modify your RTL for better structure, or reduce your clock frequency target.

Open-Source vs. Commercial EDA Tools

The Electronic Design Automation (EDA) landscape has traditionally been dominated by commercial tools with expensive licenses. However, the open-source movement has made significant strides, democratizing chip design.

Commercial Tools: The Industry Standard

Tools like Synopsys Design Compiler, Cadence Genus, and Mentor Graphics offer mature, highly optimized synthesis engines with decades of development. They provide:

• Advanced optimization algorithms proven across thousands of production designs
• Comprehensive standard cell library support
• Excellent customer support and documentation
• Integration with complete design flows (place-and-route, verification, etc.)

The tradeoff? Cost. Commercial tool licenses can run from thousands to hundreds of thousands of dollars annually, making them accessible primarily to established companies and well-funded universities.

Open-Source Tools: Democratizing Design

The open-source alternative has grown remarkably capable:

Yosys serves as the primary open-source synthesis tool. It can read Verilog, perform optimization, and map to various technology libraries. While perhaps not as aggressively optimized as commercial tools, Yosys handles real-world designs effectively and is under active development.

OpenSTA provides static timing analysis, checking your synthesized design for timing violations.

OpenROAD offers an integrated flow from synthesis through place-and-route, bringing open-source tools closer to a complete design environment.

The advantages are clear: zero licensing costs, complete transparency into tool operation, and the ability to modify tools for specific needs. The community support is growing, and for educational purposes or smaller projects, these tools are entirely viable.

Why Skywater 130nm? The Open PDK Revolution

Historically, Process Design Kits have been proprietary and subject to strict Non-Disclosure Agreements (NDAs). This created a significant barrier: you couldn't learn chip design with real manufacturing processes without industry connections.

The Skywater 130nm PDK Changes Everything

In 2020, Google partnered with Skywater Technology to release the first fully open-source PDK for a manufacturable process. The Skywater 130nm PDK provides:

• Complete standard cell libraries (thousands of pre-designed logic gates)
• I/O pad libraries for interfacing with the outside world
• Memory compilers for generating SRAM blocks
• SPICE models for transistor-level simulation
• Design rules and technology files for layout tools

Why 130nm? While not cutting-edge (modern smartphones use 5nm or smaller), 130nm is far from obsolete. It's used for:

• Microcontrollers and embedded systems
• Analog and mixed-signal designs
• Power management circuits
• Automotive electronics (where reliability matters more than raw density)
• IoT sensors and edge devices

For learning, 130nm is ideal. It's modern enough to represent real design challenges but mature enough to be thoroughly documented and understood.

The Open PDK Initiative's Broader Impact

The Skywater release sparked a movement. It enables:

• University courses teaching the complete design flow with actual manufacturable technology
• Hobbyists and startups designing custom chips without massive upfront costs
• Programs like Google's ChipIgnite offering free fabrication runs for open-source designs
• Research into new EDA algorithms with real-world test cases

This democratization parallels what Linux did for operating systems or what Arduino did for embedded systems—removing barriers and expanding access to previously exclusive knowledge.

Putting It All Together

Understanding this flow prepares you for the hands-on work ahead. You'll write RTL, simulate it to verify functionality, synthesize it to gates using Yosys and the Skywater PDK, and analyze timing to ensure your design meets specifications.

Each stage reveals different aspects of your design. Simulation shows logical correctness. Synthesis reveals area and power characteristics. Timing analysis indicates maximum operating frequency. Together, they provide a complete picture of your hardware design's feasibility.

The beauty of the open-source flow with Skywater 130nm is that you can now experience this entire journey on your own computer, with freely available tools and a real manufacturing process, learning skills directly applicable to professional chip design.

In the next sections, we'll get these tools installed and configured, then begin designing and synthesizing actual circuits. The journey from code to silicon awaits!