On-Chip Variation, Derates and Sign-Off Corners

Two identical gates on the same die never have exactly the same delay. Small differences in channel length, threshold voltage, local supply and temperature make some cells a little faster and some a little slower, even within one corner. Sign-off timing accounts for this on-chip variation (OCV) with derates: late paths are made slower and early paths faster by a few percent. For the physical designer, OCV is not just a sign-off setting. It changes which paths fail, how much the clock tree costs, and when to turn it on in the flow. This article runs real derates on the lab's routed multiplier and shows what changes.

8 min read | Intermediate

What You'll Learn

• Apply timing derates in OpenROAD and read their effect on a routed design
• Explain clock reconvergence pessimism removal (CRPR) with real numbers
• Describe how clock tree structure changes the cost of OCV
• Choose corners and derates for each stage of the flow

Corners and Variation

A corner, as in Post-Route STA: What Changes from Synthesis, moves every cell on the die the same way: at the slow corner all transistors are slow. On-chip variation describes the differences that remain between cells inside one corner. The STA tutorial explains the models in detail, in On-Chip Variation and Timing Derates, AOCV: Depth and Distance Derating and POCV and the Liberty Variation Format. In short:

• A setup check is pessimistic if the launch clock and the data path are late and the capture clock is early. A late derate above 1 slows the first two; an early derate below 1 speeds up the third.
• A hold check uses the opposite combination.
• Flat derates apply the same percentage everywhere; advanced methods make it depend on path depth, distance or each cell's own statistical data.

The Experiment

The design is the 16 x 16 multiplier routed by the lab's flow at a 10 ns clock in the typical corner, with its extracted parasitics. The timing is rerun in OpenROAD with the lab's constraints and different derates added on top:

set_timing_derate -late 1.05
set_timing_derate -early 0.95
report_checks -path_delay max -format full_clock_expanded

set_timing_derate can be limited to clock paths with -clock or data paths with -data, and to cell or net delays. The results:

A design that met timing with 0.134 ns to spare fails by 0.353 ns once 5 % of variation is assumed, and at 10 % the total negative slack is 1.630 ns. The 5 % case loses 0.487 ns of slack, which is exactly 5 % of the critical data path: the path from the launching flip-flop's clock pin to the capturing flip-flop's input is 9.736 ns long. On a long data path, the derate on the data dominates.

Why the Clock Derate Cost Nothing

The derated report shows why. The launch clock passes clkbuf_0_clk and clkbuf_3_0__f_clk and arrives at 0.346 ns with the late derate. The capture clock passes the same two buffers and arrives at 0.313 ns with the early derate. But the same physical buffers cannot be slow for one edge and fast for the other at the same time: they are one piece of silicon. STA therefore gives the difference back:

   0.001   10.313 ^ _2415_/CLK (sky130_fd_sc_hd__dfxtp_1)
   0.033   10.346   clock reconvergence pessimism
  -0.129   10.217   library setup time

The 0.033 ns credit is clock reconvergence pessimism removal (CRPR), also called common path pessimism removal, explained in Common Path Pessimism Removal. Here the whole clock path is shared except a 0.001 ns wire, so the credit cancels the clock derate almost completely. Switching CRPR off in OpenROAD with set sta_crpr_enabled 0 shows its value: the worst setup slack drops from -0.353 to -0.385 ns, and the worst hold slack from 0.929 to 0.912 ns.

What This Means for the Clock Tree

CRPR only credits the shared part of the launch and capture clock paths. After the paths split, every buffer on either branch is derated in the pessimistic direction. Two consequences for CTS in OpenROAD and the floorplan:

• Related flip-flops should share as much of the tree as possible. Flip-flops that talk to each other, placed close together, end up on the same branch, so their critical paths have a long common clock path and a small OCV penalty. In the multiplier, the critical path's two flip-flops share every buffer.
• Long separate branches cost margin. A path between flip-flops at opposite ends of a large chip has clock branches that split near the root. Each branch might be 1 ns long; at 5 % each side, the uncredited pessimism approaches 0.1 ns, before any data path derate.

The same reasoning explains why a low-latency clock tree helps under OCV: the derate is a percentage of the delay, so a shorter tree has less delay to derate.

When to Turn Derates On

If the implementation tools optimize without derates and sign-off applies them, the design that looked closed fails at the end, as the multiplier did. Common practice:

• From placement on, timing optimization runs with the sign-off derates, or with a clock uncertainty that covers them early in the flow, before the clock tree exists.
• After CTS, propagated clocks and CRPR make the clock part of the derate accurate, and the extra uncertainty can be reduced.
• After routing, extracted parasitics and the real derates give sign-off numbers; the fixes of Fixing Setup in Layout then work against the right target.

Derate values are not chosen by the physical designer. They come from the foundry or library team, sometimes as a flat percentage, often as depth-dependent tables or statistical library data, and the sign-off methodology fixes them per corner.

Corners in the Flow

Derates sit on top of corners. A typical set for sign-off covers setup at the slow corner, hold at the fast corner, and each of these at the RC corners of the interconnect described in RC Corners, across the operating modes of Multi-Corner Multi-Mode Analysis. Running all combinations through every optimization step is slow, so flows pick a few dominant scenarios for placement and CTS and run the full set after routing. The multiplier's own three-corner results are in Post-Route STA: What Changes from Synthesis.

Running It in ChipVerify Lab

The lab's flow reports timing without derates. With PRO, a custom script can add set_timing_derate before the final timing reports, or before repair_timing to make the optimization see them. The numbers in this article come from rerunning timing on the lab's routed multiplier in the same OpenROAD version, outside the lab.

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