SystemVerilog Quick Refresher

disable fork kills ALL child threads, including those from outer scopes. To limit scope, wrap the fork in a named begin...end block and disable that block instead.

Classes (OOP for Verification)

class Transaction;
  // Properties
  rand  bit [7:0]  addr;        // randomizable
  rand  bit [31:0] data;
  randc bit [3:0]  id;          // cyclic random — covers all values before repeating
  bit              is_write;
  static int       count = 0;   // shared across all instances

  // Constraints
  constraint addr_range { addr inside {[8'h00:8'h7F]}; }
  constraint data_align { data[1:0] == 2'b00; }

  // Constructor
  function new(bit is_write = 0);
    this.is_write = is_write;
    count++;
  endfunction

  // Methods
  function void display();
    $display("Txn id=%0d addr=0x%02h data=0x%08h wr=%0b",
             id, addr, data, is_write);
  endfunction

  // Virtual method — can be overridden by subclass
  virtual function bit is_valid();
    return (addr != '0);
  endfunction

  // Copy
  function Transaction copy();
    Transaction t = new();
    t.addr     = this.addr;
    t.data     = this.data;
    t.id       = this.id;
    t.is_write = this.is_write;
    return t;
  endfunction
endclass

// Inheritance
class WriteTransaction extends Transaction;
  rand bit [3:0] byte_enable;

  constraint be_valid { $countones(byte_enable) inside {1, 2, 4}; }

  function new();
    super.new(1);              // call parent constructor
  endfunction

  // Override virtual method
  function bit is_valid();
    return (super.is_valid() && byte_enable != 0);
  endfunction
endclass

// Usage
Transaction t = new();
t.randomize();                 // randomize with constraints
t.display();

WriteTransaction wt = new();
wt.randomize() with { addr < 8'h40; };  // inline constraint

Polymorphism

// Virtual methods enable polymorphism
Transaction t;
WriteTransaction wt = new();
t = wt;                        // parent handle pointing to child object
t.is_valid();                  // calls WriteTransaction::is_valid() (virtual dispatch)

// $cast for downcasting
WriteTransaction wt2;
if ($cast(wt2, t))             // runtime check: is t actually a WriteTransaction?
  wt2.byte_enable = 4'hF;

Parameterized Classes

class Stack #(type T = int, int DEPTH = 32);
  T data[$:DEPTH-1];

  function void push(T val);
    if (data.size() < DEPTH) data.push_back(val);
  endfunction

  function T pop();
    return data.pop_front();
  endfunction

  function int size();
    return data.size();
  endfunction
endclass

Stack #(bit [7:0], 64) byte_stack = new();
Stack #(Transaction)   txn_stack  = new();

Constrained Randomization

class Packet;
  rand  bit [7:0]  length;
  rand  bit [15:0] addr;
  rand  bit [7:0]  payload[];
  randc bit [2:0]  channel;      // cyclic — all values visited before repeat

  // Simple constraints
  constraint len_range   { length inside {[1:64]}; }
  constraint addr_align  { addr[1:0] == 2'b00; }      // 4-byte aligned
  constraint payload_sz  { payload.size() == length; }

  // Weighted distribution
  constraint len_dist {
    length dist {
      [1:8]   := 50,     // equal weight per value in range
      [9:32]  :/ 30,     // weight divided among values in range
      [33:64] := 20
    };
  }

  // Implication
  constraint wr_addr {
    (channel == 0) -> addr inside {[16'h0000:16'h0FFF]};
  }

  // Conditional constraint
  constraint cond_c {
    if (length > 32) addr > 16'h1000;
    else             addr < 16'h1000;
  }

  // Foreach on arrays
  constraint ordered {
    foreach (payload[i])
      if (i > 0) payload[i] >= payload[i-1];
  }

  // Solve order — control randomization order
  constraint order { solve length before addr; }
endclass

// Randomization calls
Packet p = new();
assert(p.randomize());                    // basic randomize
assert(p.randomize() with {              // inline constraints (added on top)
  length < 16;
  addr == 16'h0100;
});

// Constraint control
p.constraint_mode(0);                     // disable ALL constraints
p.len_range.constraint_mode(0);           // disable specific constraint
p.rand_mode(0);                           // disable ALL randomization
p.addr.rand_mode(0);                      // disable specific field randomization

// Pre/post randomize callbacks
class SmartPacket extends Packet;
  function void pre_randomize();
    // called before randomize()
  endfunction

  function void post_randomize();
    // called after randomize() — compute CRC, etc.
  endfunction
endclass

Assertions (SVA)

Immediate Assertions

// Simple immediate assertion — checked procedurally
always_comb begin
  assert (state != ILLEGAL_STATE) else $error("Illegal state reached");
end

// With action blocks
always_ff @(posedge clk) begin
  assert (fifo_count <= DEPTH)
    $display("FIFO OK, count=%0d", fifo_count);   // pass action
  else
    $fatal(1, "FIFO overflow! count=%0d", fifo_count); // fail action
end

// Deferred assertion — checked at end of time step (avoids glitches)
always_comb begin
  assert #0 (onehot(grant)) else $error("Grant not one-hot");
end

Concurrent Assertions

// Property — a reusable temporal expression
property p_req_ack;
  @(posedge clk) disable iff (!rst_n)
  req |-> ##[1:3] ack;              // if req, ack must come within 1-3 cycles
endproperty

assert property (p_req_ack)
  else $error("Req not acknowledged within 3 cycles");

// Sequence — a pattern of events over time
sequence s_handshake;
  req ##1 ack ##1 !req ##1 !ack;    // four-cycle handshake
endsequence

property p_handshake;
  @(posedge clk) disable iff (!rst_n)
  req |-> s_handshake;
endproperty

assert property (p_handshake);

SVA Operators

Common Assertion Patterns

// Request must be acknowledged
assert property (@(posedge clk) disable iff (!rst_n)
  req |-> ##[1:5] ack
);

// Signal must be stable while valid
assert property (@(posedge clk) disable iff (!rst_n)
  valid |-> $stable(data)
);

// Two signals are mutually exclusive
assert property (@(posedge clk) disable iff (!rst_n)
  not (signal_a && signal_b)
);

// Data must change after write
assert property (@(posedge clk) disable iff (!rst_n)
  (wr_en && addr == TARGET) |=> (rdata == $past(wdata))
);

// No back-to-back requests
assert property (@(posedge clk) disable iff (!rst_n)
  req |=> !req
);

// Cover — check that a scenario CAN occur (not that it must)
cover property (@(posedge clk) req ##1 ack);

// Assume — constrain inputs in formal verification
assume property (@(posedge clk) $onehot0(req));

Functional Coverage

// Covergroup — tracks value coverage during simulation
covergroup cg_bus @(posedge clk);
  option.per_instance = 1;

  // Coverpoint — which values were seen
  cp_addr: coverpoint addr {
    bins low    = {[0:63]};
    bins mid    = {[64:191]};
    bins high   = {[192:255]};
    bins zero   = {0};
    illegal_bins reserved = {[240:255]};   // error if hit
    ignore_bins unused    = {[200:239]};   // don't count
  }

  cp_cmd: coverpoint cmd {
    bins read  = {READ};
    bins write = {WRITE};
  }

  cp_len: coverpoint length {
    bins short_pkt  = {[1:8]};
    bins medium_pkt = {[9:32]};
    bins long_pkt   = {[33:64]};
    bins powers[]   = {1, 2, 4, 8, 16, 32, 64}; // one bin per value
  }

  // Cross coverage — combinations of coverpoints
  addr_x_cmd: cross cp_addr, cp_cmd;

  // Transition coverage
  cp_state: coverpoint state {
    bins idle_to_run  = (IDLE => RUN);
    bins run_to_done  = (RUN  => DONE);
    bins any_to_idle  = (RUN, DONE => IDLE);
  }
endgroup

// Instantiate and sample
cg_bus bus_cov = new();

// Explicit sampling (alternative to automatic @(posedge clk))
covergroup cg_txn;
  coverpoint txn.addr;
  coverpoint txn.data;
endgroup

cg_txn txn_cov = new();
// ... later ...
txn_cov.sample();              // manually trigger sampling

// Query coverage
$display("Coverage: %.1f%%", bus_cov.get_coverage());

Processes & Synchronization

Events

event done;
event error;

// Trigger
-> done;                    // trigger event (non-blocking)
->> done;                   // non-blocking trigger (for use in always_ff)

// Wait
@(done);                    // wait for trigger
wait(done.triggered);       // level-sensitive — doesn't miss same-timestep trigger

Mailboxes

// Typed mailbox — thread-safe FIFO
mailbox #(Transaction) mbx = new(16);   // bounded: max 16 entries
mailbox #(Transaction) ubx = new();     // unbounded

// Producer
Transaction t = new();
t.randomize();
mbx.put(t);                   // blocking if full
mbx.try_put(t);               // non-blocking, returns 0 if full

// Consumer
Transaction rx;
mbx.get(rx);                  // blocking if empty
mbx.try_get(rx);              // non-blocking, returns 0 if empty
mbx.peek(rx);                 // get without removing

int n = mbx.num();            // number of entries

Semaphores

semaphore sem = new(1);        // 1 key = mutex

// Acquire
sem.get(1);                    // blocking — wait for key
sem.try_get(1);                // non-blocking, returns 0 if unavailable

// Release
sem.put(1);                    // return key

// Example: mutual exclusion
task automatic critical_section();
  sem.get(1);
  // ... exclusive access ...
  sem.put(1);
endtask

Virtual Interfaces

// Virtual interface — a handle to an interface instance
// Allows class-based testbenches to drive/sample physical signals

class Driver;
  virtual axi_lite_if vif;     // virtual interface handle

  function new(virtual axi_lite_if vif);
    this.vif = vif;
  endfunction

  task run();
    forever begin
      @(posedge vif.clk);
      vif.awaddr  <= txn.addr;
      vif.awvalid <= 1'b1;
      @(posedge vif.clk iff vif.awready);
      vif.awvalid <= 1'b0;
    end
  endtask
endclass

// In testbench top
module tb;
  logic clk, rst_n;
  axi_lite_if u_if (.clk, .rst_n);
  axi_slave   dut  (.bus(u_if.slave));

  Driver drv = new(u_if);     // pass interface to class
  initial drv.run();
endmodule

Classes cannot have ports, so virtual interface is the bridge between class-based verification (OOP) and the signal-level world of modules. Every UVM component uses virtual interfaces to access DUT signals.

Program Block

// program — separates testbench from DUT timing
// Executes in the "reactive" region (after all design updates)
program automatic test (
  input logic clk,
  bus_if.driver drv_if
);
  initial begin
    repeat (10) @(posedge clk);
    drv_if.driver_cb.data  <= 8'hAB;
    drv_if.driver_cb.valid <= 1'b1;
    @(drv_if.driver_cb);
    drv_if.driver_cb.valid <= 1'b0;
    $display("Test complete");
  end
endprogram

The program block avoids race conditions by scheduling testbench code in the Reactive region, after all RTL always blocks have executed. In UVM-based flows, program blocks are less common since UVM handles phasing internally.

Generate Blocks — SystemVerilog Style

// generate/endgenerate keywords are optional in SystemVerilog
// Loop generate
for (genvar g = 0; g < N; g++) begin : stage
  assign pipe[g+1] = pipe[g] & enable[g];
end

// Conditional generate
if (USE_PARITY) begin : gen_par
  parity_checker u_par (.data(bus), .par(par_bit));
end else begin : gen_nopar
  assign par_ok = 1'b1;
end

// Case generate
case (IMPL)
  "FAST":    fast_adder  u_add (.*);
  "SMALL":   small_adder u_add (.*);
  default:   basic_adder u_add (.*);
endcase

Loops — Enhanced

// C-style for loop (declare loop variable inline)
always_comb begin
  parity = 1'b0;
  for (int i = 0; i < 8; i++) begin
    parity ^= data[i];
  end
end

// foreach — iterate over arrays
int arr[4] = '{10, 20, 30, 40};
foreach (arr[i]) begin
  $display("arr[%0d] = %0d", i, arr[i]);
end

// foreach on multidimensional arrays
int matrix[3][4];
foreach (matrix[i, j]) begin
  matrix[i][j] = i * 4 + j;
end

// do...while
int count = 0;
do begin
  // body executes at least once
  count++;
end while (count < 10);

// break and continue
for (int i = 0; i < 100; i++) begin
  if (skip_condition) continue;   // skip rest of this iteration
  if (stop_condition) break;      // exit loop entirely
  // ...
end

System Tasks & Functions — SystemVerilog Additions

Severity System Tasks

$info("Informational message");            // severity: info
$warning("Something unusual: %0d", val);   // severity: warning
$error("Protocol violation at %0t", $time); // severity: error
$fatal(1, "Unrecoverable: FIFO overflow"); // severity: fatal (stops simulation)
// $fatal first argument sets the diagnostic level (0 prints nothing, 1 time and location, 2 adds statistics); the simulation always finishes

Array Query Functions

int arr[4][8];

$dimensions(arr)       // 2 (number of dimensions)
$left(arr, 1)          // 0 (left bound of dimension 1)
$right(arr, 1)         // 3 (right bound of dimension 1)
$low(arr, 1)           // 0
$high(arr, 1)          // 3
$size(arr, 1)          // 4 (size of dimension 1)
$increment(arr, 1)     // 1 or -1 depending on range direction
$bits(arr)             // total bits

Type & Conversion

$typename(var)          // returns type name as string
$itor(int_val)          // integer to real
$rtoi(real_val)         // real to integer
$signed(val)            // cast to signed
$unsigned(val)          // cast to unsigned
$bitstoreal(bits)       // bit pattern to real
$realtobits(r)          // real to bit pattern

Direct Programming Interface (DPI)

// Import C function into SystemVerilog
import "DPI-C" function int c_sqrt(input int val);
import "DPI-C" function void c_print(input string msg);
import "DPI-C" context function void c_callback();

// Export SystemVerilog function to C
export "DPI-C" function sv_get_data;

function int sv_get_data(input int addr);
  return mem[addr];
endfunction

// Usage
initial begin
  int result = c_sqrt(144);    // calls C function
  $display("sqrt(144) = %0d", result);
end

DPI enables calling C/C++ functions from SystemVerilog and vice versa. Use it for complex math, file parsing, or connecting to external models. The context keyword allows the C function to call back into SystemVerilog.

Compiler Directives — Additions

// Same as Verilog, plus:
`begin_keywords "1800-2012"     // restrict to specific SV version keywords
`end_keywords

`__FILE__                       // current filename (string)
`__LINE__                       // current line number (integer)

`pragma protect begin           // IP encryption
`pragma protect end

Common RTL Patterns — SystemVerilog Style

FSM with Enum

typedef enum logic [1:0] {
  IDLE = 2'b00,
  RUN  = 2'b01,
  DONE = 2'b10
} state_e;

state_e state, next_state;

always_ff @(posedge clk or negedge rst_n) begin
  if (!rst_n) state <= IDLE;
  else        state <= next_state;
end

always_comb begin
  next_state = state;
  busy  = 1'b0;
  valid = 1'b0;
  unique case (state)
    IDLE: if (start) next_state = RUN;
    RUN:  begin
      busy = 1'b1;
      if (done) next_state = DONE;
    end
    DONE: begin
      valid = 1'b1;
      next_state = IDLE;
    end
    default: next_state = IDLE;
  endcase
end

Parameterized FIFO

module sync_fifo #(
  parameter type DATA_T = logic [7:0],
  parameter int  DEPTH  = 16
)(
  input  logic  clk,
  input  logic  rst_n,
  input  logic  wr_en,
  input  DATA_T wr_data,
  input  logic  rd_en,
  output DATA_T rd_data,
  output logic  full,
  output logic  empty
);
  localparam int ADDR_W = $clog2(DEPTH);

  DATA_T mem [DEPTH];
  logic [ADDR_W:0] wr_ptr, rd_ptr;       // extra bit for full/empty

  assign full  = (wr_ptr[ADDR_W] != rd_ptr[ADDR_W]) &&
                 (wr_ptr[ADDR_W-1:0] == rd_ptr[ADDR_W-1:0]);
  assign empty = (wr_ptr == rd_ptr);

  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      wr_ptr <= '0;
      rd_ptr <= '0;
    end else begin
      if (wr_en && !full) begin
        mem[wr_ptr[ADDR_W-1:0]] <= wr_data;
        wr_ptr <= wr_ptr + 1'b1;
      end
      if (rd_en && !empty) begin
        rd_ptr <= rd_ptr + 1'b1;
      end
    end
  end

  assign rd_data = mem[rd_ptr[ADDR_W-1:0]];
endmodule

AXI-Style Handshake

// Valid/ready handshake — transfer occurs when both asserted
always_ff @(posedge clk or negedge rst_n) begin
  if (!rst_n) begin
    valid <= 1'b0;
    data  <= '0;
  end else if (valid && ready) begin
    // Transfer accepted — load next
    valid <= next_valid;
    data  <= next_data;
  end else if (!valid) begin
    // Load new data when idle
    valid <= next_valid;
    data  <= next_data;
  end
end

// Assertion to verify protocol
assert property (@(posedge clk) disable iff (!rst_n)
  valid && !ready |=> valid && $stable(data)
) else $error("Valid data changed without ready");

Packed Struct Bus

package bus_pkg;
  typedef enum logic [1:0] {
    CMD_READ  = 2'b00,
    CMD_WRITE = 2'b01,
    CMD_NOP   = 2'b10
  } cmd_e;

  typedef struct packed {
    cmd_e         cmd;
    logic [15:0]  addr;
    logic [31:0]  data;
    logic [3:0]   strobe;
  } bus_req_t;

  typedef struct packed {
    logic [31:0]  data;
    logic [1:0]   resp;
    logic         valid;
  } bus_resp_t;
endpackage

module bus_master
  import bus_pkg::*;
(
  output bus_req_t  req,
  input  bus_resp_t resp
);
  always_comb begin
    req.cmd    = CMD_WRITE;
    req.addr   = 16'h1000;
    req.data   = 32'hDEAD_BEEF;
    req.strobe = 4'hF;
  end
endmodule

Edge Detector (SystemVerilog Style)

logic sig_q;
always_ff @(posedge clk) sig_q <= sig;

logic rising;  assign rising  = sig & ~sig_q;
logic falling; assign falling = ~sig & sig_q;

// Or use $rose/$fell in assertions and procedural code
always_ff @(posedge clk)
  if ($rose(sig)) count <= count + 1;

UVM Essentials (Quick Reference)

SystemVerilog classes power the Universal Verification Methodology. Here are the key building blocks.

UVM Component Hierarchy

Minimal UVM Skeleton

// Sequence item
class my_txn extends uvm_sequence_item;
  `uvm_object_utils(my_txn)

  rand bit [7:0] addr;
  rand bit [31:0] data;

  function new(string name = "my_txn");
    super.new(name);
  endfunction
endclass

// Sequence
class my_seq extends uvm_sequence #(my_txn);
  `uvm_object_utils(my_seq)

  function new(string name = "my_seq");
    super.new(name);
  endfunction

  task body();
    my_txn txn;
    repeat (10) begin
      txn = my_txn::type_id::create("txn");
      start_item(txn);
      assert(txn.randomize());
      finish_item(txn);
    end
  endtask
endclass

// Driver
class my_driver extends uvm_driver #(my_txn);
  `uvm_component_utils(my_driver)
  virtual bus_if vif;

  function new(string name, uvm_component parent);
    super.new(name, parent);
  endfunction

  task run_phase(uvm_phase phase);
    forever begin
      seq_item_port.get_next_item(req);
      // drive signals via vif
      @(posedge vif.clk);
      vif.addr <= req.addr;
      vif.data <= req.data;
      @(posedge vif.clk);
      seq_item_port.item_done();
    end
  endtask
endclass

Synthesis Golden Rules — SystemVerilog Edition

• Use logic instead of wire/reg — except for multi-driver nets
• Use always_comb, always_ff, always_latch — never plain always
• Use = in always_comb, <= in always_ff — the convention that lint tools check
• Use unique case or priority case — replaces full_case/parallel_case
• Use typedef enum logic [N:0] for FSM states — explicit encoding width
• Use packed structs for bus bundles — cleaner than raw vectors
• Use packages for shared types and parameters — avoid `defines
• Use interfaces for complex bus protocols — reduce port clutter
• Use $clog2() for address widths
• Use '0, '1, 'x, 'z for context-width fill
• `default_nettype none at the top of every file
• One module per file, filename matches module name

What Is Synthesizable?

Common Pitfalls