From Block to Chip: What the Top Level Adds

Everything in the earlier chapters happened inside one block: a die area, a core, rows of standard cells and a power grid fed from straps at the edge. A real chip adds a layer around all of that. It needs I/O cells that drive signals off the die and protect it from static discharge, pads or bumps where the package connects, supply pads that bring current in, and a top-level floorplan that places the blocks inside the pad ring. This article describes what the top level adds, using the open Caravel harness chip, built in sky130, as a real example with real dimensions.

7 min read | Intermediate

What You'll Learn

• Name what a full chip has that a block does not
• Read a chip-level floorplan: pad ring, core, blocks and supply domains
• Describe the order of the chip-level steps
• Explain why I/O and package decisions are made early

Block Versus Chip

In the lab, the multiplier's pins are simply metal shapes on the die edge, and the power grid's straps are assumed to be fed from outside. That is the right model for a block that will sit inside a larger chip. Its pins connect to other blocks' wires, and its supply comes from the parent's grid.

A chip has nothing outside it except the package. Every signal that leaves it must be driven strongly enough to charge a board trace, at a voltage another chip understands. Every input must survive whatever the outside world applies to it, including electrostatic discharge from a person or a machine. All the supply current has to enter through a limited number of connections. These jobs are done by components that a block never sees:

• I/O cells. Large cells with output drivers, input receivers, level shifters and ESD protection, described in I/O Cells: Drivers, Receivers and Level Shifting.
• The pad ring. I/O cells, supply pads, corner cells and filler cells placed edge to edge around the die, forming continuous supply buses. See Building the Pad Ring.
• Pads or bumps. The metal openings where bond wires or solder bumps attach.
• Supply pads and their placement. How many are needed and where, covered in Power and Ground Pads: How Many and Where.
• The package. Its connections and parasitics feed back into the floorplan, as Chip-Package Co-Design explains.

A Real Chip: Caravel

Caravel is the harness chip that carries user designs on the open sky130 shuttles. Its layout is public, so its numbers can be read directly from the design files: the die is 3,588 x 5,188 um, or 18.6 mm².

The floorplan has three parts:

• The pad ring around the edge, about 200 um deep: the sky130 I/O cells are 200 um tall, and the corner cells 200 x 204 um. The core inside it is 3,165 x 4,767 um, so the ring takes 3.5 mm², 19 % of the die.
• The management area at the bottom of the core: a small processor with its memories, a housekeeping block, clocking and a power-on reset.
• The user area, 2,920 x 3,520 um, which is 55 % of the die. A user's design is hardened as one block of exactly this size, with its pins at fixed positions on its edges.

For a user of Caravel, the user area is just a block with a fixed outline and fixed pins, like the blocks of Hierarchical Physical Design. Caravel's own designers did the chip-level work: the pad ring, the routing from the ring to the user area, the supply domains and the package.

Supply Domains at the Chip Level

A block has one VDD and one VSS. A chip usually has several supplies, and the pad ring carries them all. Caravel's pinout lists:

The core logic runs at 1.8 V on thin-oxide transistors, while the I/O runs at 3.3 V on thick-oxide transistors that tolerate it. Separate supplies also keep the noise of switching outputs away from the core, and the noise of digital logic away from analog circuits. Each domain needs its own supply pads, its own segment of bus in the pad ring, and ESD protection between it and every other domain.

The Chip-Level Steps

• Package and pin list. The package type, its number of pins or balls, and which signal and supply goes where. This comes first because it fixes how many pads the die needs and on which side.
• Pad ring. I/O cells and supply pads in their slots, corners, fillers, and the bond pads or bumps.
• Top floorplan. Blocks and macros placed inside the ring, close to the I/Os they use, with channels for top-level routing.
• Top power grid. Rings and straps from the supply pads to the core and into every block's own grid.
• Blocks. Each block is implemented as in the earlier chapters, with pin positions and timing budgets from the top level.
• Top-level routing and chip finishing. Routes between blocks and to the I/O cells, then seal ring, fill, logos and the final checks of Physical Sign-Off Checklist, run on the full chip.

The order matters because each decision limits the next. A package with too few balls cannot be fixed by the floorplan, and a pad ring with too few supply pads cannot be fixed by the power grid.

What Changes for the Physical Designer

Several topics from the block chapters look different at the top level:

• Pin placement becomes pad placement. A block pin can move by a few micrometres; an I/O cell moves in slots of its own width, and its position is tied to the package.
• The power grid starts at the supply pads, not at an assumed source. The IR drop of IR Drop: Static and Dynamic includes the path from pad to block, and the pad count and spacing become design variables.
• Timing includes the I/O cells, whose delays depend on the board load, and the long top-level routes between blocks.
• Verification adds checks that only make sense for a chip: ESD paths for every pad, latch-up rules near the I/O, and a full-chip LVS that includes the pad cells.

Running It in ChipVerify Lab

At the time of writing, the lab's Place and Route flow implements a block: it has no I/O cell library, pad ring or bumps. The articles of this chapter use the sky130 I/O library files and the public Caravel layout as their data. With PRO, you can still prepare a block for a fixed-outline slot like Caravel's user area: set the die area in the panel and keep the pins on the edges where the parent expects them.

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