Advanced Nodes: FinFETs, Multi-Patterning and Via Rules

Advanced process nodes change physical design in ways a 130 nm process like sky130 never shows: transistors built from fins in fixed steps, metal pitches too fine to print in one exposure, routing that may only run in one direction, and vias whose resistance and rules dominate the wiring. This article explains these changes and uses the routed 16x16 multiplier in sky130 as the point of comparison: what the router did there that an advanced node would not allow.

7 min read | Intermediate

What You'll Learn

• Explain how FinFETs change cell design and sizing
• Describe multi-patterning and its effect on routing
• Explain unidirectional routing and why wrong-way jogs disappear
• Describe why vias and thin wires become the limit at advanced nodes

FinFETs: Width in Steps

In a planar transistor, as in sky130, the channel is a flat region whose width the cell designer chooses freely; a stronger cell simply has wider transistors. A FinFET wraps the gate around thin vertical fins of silicon, which controls the channel much better at short gate lengths and cuts leakage. The width of a FinFET is set by the number of fins, so drive strength comes in steps of one fin.

That quantization reaches physical design. Cell heights are counted in metal tracks, cell widths in gate pitches, and every cell variant is a choice of fins per transistor. The cell library becomes more regular, and the placer works on a stricter grid.

For comparison, a sky130 hd site is 0.46 um wide and 2.72 um tall, which is 8 met1 pitches of 0.34 um. Within that height the cell designer could draw transistors of any width.

Multi-Patterning

Lithography can print lines only down to a minimum pitch in one exposure; for the 193 nm immersion lithography used for many years, that limit is around 80 nm. Finer pitches are made by splitting one layer's shapes into two or more masks, each printed separately: double patterning, triple patterning, or self-aligned methods that build the fine lines from a coarser pattern. Each mask is called a colour.

• Two shapes on the same colour must keep the larger single-exposure spacing; on different colours they may be closer.
• The router and the checks must assign colours so that no conflict remains, much like colouring a map.
• The two masks can be shifted slightly against each other, so the spacing and coupling between wires depend on their colours, and extraction has to account for it.

sky130's smallest metal pitch, 0.34 um on met1, is far above this limit, so every layer is printed in one exposure and no colouring is needed.

One Direction per Layer

At fine pitches, a short wire segment at right angles to the layer's preferred direction is hard to print and to check. Advanced nodes therefore make the lower metal layers strictly unidirectional: every wire on a layer runs in one direction, and a change of direction always goes through a via to the next layer.

sky130 only prefers a direction. On the routed multiplier:

The router used almost 1,400 vertical segments on met1, on average 0.42 um long: short jogs that save a via. With unidirectional rules each of those would become a via up to met2 and back, or a different route, which costs vias, tracks and resistance.

Vias and Thin Wires

As wires get narrower, their resistance per micrometre rises quickly: the cross-section shrinks, and at very small widths the electrons scatter more at the edges and grain boundaries. Vias shrink too, and a single via cut can have a resistance comparable to a long piece of wire. At advanced nodes:

• Via resistance becomes a large part of the delay of short nets, and the router prefers fewer layer changes.
• Redundant vias (two cuts where one would do) are inserted wherever there is room, for lower resistance and better yield.
• Via pillars, stacks of vias with wider metal on several layers, give critical nets a low-resistance path up to the thick upper layers.
• Via rules become more complex: cut classes, enclosure depending on the neighbours, and spacing between cuts on different layers.

In the sky130 multiplier, every signal via is one of four predefined single-cut vias: 4,339 L1M1_PR_MR (li1 to met1), 4,069 M1M2_PR, 98 M2M3_PR and 4 M3M4_PR. The router never needed double cuts or pillars. The detailed router's warning that it skips a rule for mcon, shown in Detailed Routing, is a small sign of the more complex cut rules in newer technology files.

What Else Changes

• Local interconnect. Advanced nodes use dedicated layers below metal 1 to connect transistors inside cells. sky130's li1 layer plays a similar role.
• Cell-level DFM rules. Cells must line up on fixed grids, with fill and dummy gates at their edges, and some cell combinations are not allowed side by side.
• Variation. Smaller devices vary more, so timing uses statistical margins and location-dependent derates instead of a single corner margin, as in On-Chip Variation, Derates and Sign-Off Corners.
• Power density. More transistors per area make IR drop and EM harder, and backside power delivery moves the power grid under the transistors in the newest nodes.

Running It in ChipVerify Lab

The lab's flow uses sky130, so none of the advanced node rules apply. In the layout viewer, zoom into met1 and look for short vertical segments: those are the wrong-way jogs an advanced node would forbid. The technology LEF, described in Technology LEF, shows the simple single-exposure rules that make them legal here.

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