Analog and Mixed-Signal Blocks in a Digital Chip

Most chips are not purely digital. A data converter, a PLL, a power-on reset, a bandgap reference or a temperature sensor sits among the standard cells, built by analog designers as a hard macro. These blocks work with small voltages and are disturbed by exactly what digital logic produces in abundance: switching noise on the supplies and in the substrate. Placing and connecting them is the physical designer's job, and the floorplan decides how quiet their environment is. This article covers the noise paths, the isolation techniques, and the rules for integrating an analog macro into a digital chip.

7 min read | Advanced

What You'll Learn

• Describe how digital noise reaches analog circuits
• Explain guard rings, deep n-wells and separate supplies
• Plan the placement and routing around an analog macro
• List the checks specific to mixed-signal integration

How Digital Noise Reaches Analog Circuits

Thousands of gates switching on a clock edge produce current spikes. They reach a sensitive analog block through three paths:

• Shared supplies. Digital current through the supply's resistance and inductance moves the supply voltage, the IR drop and ground bounce of Power and Ground Pads: How Many and Where. An analog block on the same supply sees all of it.
• The substrate. The body terminal of every bulk transistor connects to the substrate or a well through a relatively resistive contact. Current injected into the substrate, by capacitive coupling through junctions or by impact ionization, moves the local body voltage, and through the body effect the threshold voltages of nearby transistors. In a mixed-signal chip, the noise of the digital ground travels to the analog circuits through the shared substrate.
• Coupling between wires. A digital wire running next to or over an analog net couples into it through their capacitance, as in Crosstalk, Shielding and Non-Default Rules.

Isolation Techniques

The standard advice is to separate analog circuits physically from digital ones and protecting them with guard rings connected to a quiet analog supply:

• Guard rings. Continuous rings of substrate or well contacts around the circuit to protect. A p+ ring tied to the quiet ground collects stray carriers in the substrate before they reach the transistors inside; an n-well ring tied to a supply adds a second barrier. Double guard rings are the conservative choice, the same structure recommended around I/O output transistors against latch-up.
• Plenty of substrate contacts in both digital and analog areas, giving the substrate a low-resistance path to its supply so injected current does not build up voltage.
• Triple wells. Twin-tub or triple-well processes and SOI experience much less substrate coupling because transistors sit in their own wells. sky130 has a deep n-well layer, DNM in its mask list from From GDSII to Masks, which places a p-well with its nMOS transistors inside an n-type tub, separated from the shared substrate.
• Separate supplies. Analog blocks get their own supply and ground pads, ring buses and grid, as Caravel does with its vdda and vssa supplies for analog circuits, separate from the 1.8 V digital ones.

Floorplanning an Analog Macro

• Distance. Put the analog block at the edge of the core, often in a corner, near its own pads and as far as practical from the noisiest digital logic: clock drivers, wide buses, high-activity datapaths.
• Keep-out band. A halo around the macro, from Macro Placement: Halos and Channels, keeps standard cells away and leaves room for the guard rings.
• Routing blockages. Digital routes must not cross over the macro on the layers it uses or on the layers just above its sensitive nodes; the macro's LEF usually declares obstructions, and the floorplan adds blockages from Placement Blockages and Keep-Out Regions where it does not.
• Clock tree. Keep clock buffers and clock wires away; they switch every cycle at full strength.
• Analog pads. Analog pads connect directly to the analog circuits without digital buffers, and that their ESD protection is kept small so it does not limit bandwidth. Place them next to the macro so the analog signal wires are short.

The sky130 GPIO cell, from I/O Cells: Drivers, Receivers and Level Shifting, shows another option: it has two analog buses, AMUXBUS_A and AMUXBUS_B, that run through the pad ring, and analog pins that connect the pad to them. An analog signal can travel along the ring to the pad that needs it instead of crossing the digital core.

Routing Analog Signals

• Shielding. Sensitive analog nets get ground shields on both sides, and sometimes above and below, using the non-default rules and shielding of the crosstalk article.
• Width and resistance. Reference currents and sense lines are routed wide, because their resistance matters and their currents may be small but must be precise.
• Symmetry. Differential signals are routed as matched pairs, side by side, with the same length and the same neighbours.
• Fill. Metal fill changes the capacitance of nearby wires. Analog blocks often have fill exclusion areas or require a uniform, symmetric fill pattern, coordinated with Filler Cells, Metal Fill and Density Rules.

Boundaries Between Analog and Digital

Every signal between the analog and digital domains crosses a supply boundary. Digital control bits going into an analog block may need level shifting, as in Multi-Voltage Implementation, and a buffer powered by the analog supply at the input so the digital edge does not inject noise directly. Outputs from the analog side, such as comparator results, are synchronized in the digital domain, and their timing is constrained at the macro boundary with the macro's own timing model. The ESD checks of ESD Protection for Physical Designers also apply: every crossing between separate grounds needs a discharge path.

Checks Specific to Mixed-Signal Chips

• LVS with the analog devices, including resistors, capacitors and devices in deep n-well, which need the right rule deck options.
• Guard ring continuity and connection to the intended quiet supplies.
• No digital routing over the analog macro's restricted area.
• Correct supplies for every cell at the boundary.
• Simulation of the analog block with the extracted parasitics of the real layout around it, which the analog designers usually run.

Running It in ChipVerify Lab

At the time of writing, the lab's flow is digital only: it places standard cells and the SRAM macro of Macro Placement: Halos and Channels, but has no analog macros, guard rings or separate supplies. The halo and blockage techniques of that article are the same ones used to protect an analog macro. The sky130 details come from the PDK and Caravel design files.

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