The RTL-to-GDSII Flow

The RTL-to-GDSII flow is the chain of steps that takes a Verilog description and produces the GDSII file a foundry turns into masks. Front-end steps such as synthesis decide the logic. Back-end steps, physical design, decide the geometry. This article walks one small design, an 8-bit counter, through every step of the flow ChipVerify Lab runs, and shows what each step adds, with a picture of the layout after each one.

8 min read | Beginner

What You'll Learn

• List the steps from RTL to GDSII in order
• Describe what each step adds to the design
• Match each step to the OpenROAD command that performs it
• Read a layout picture at each stage of the flow

The Steps and Their Commands

Each box is a step, and next to it is the command that does it in the lab's flow. Commercial tools use different command names, but the order is the same. Synthesis is not part of physical design, but it produces the netlist that physical design starts from, and its choice of cells affects everything afterwards.

The design used here is a plain 8-bit counter with an enable and a synchronous reset:

module counter8 (
  input            clk,
  input            rst,
  input            en,
  output reg [7:0] q
);
  always @(posedge clk) begin
    if (rst)
      q <= 8'd0;
    else if (en)
      q <= q + 8'd1;
  end
endmodule

Synthesis with the sky130 high-density library maps it to 28 cells: 8 dfxtp_1 flip-flops and 20 logic gates, 280.3 um² in total. The clock period is 5 ns and the target utilization 50 %.

One Design, Four Snapshots

1. Floorplan

initialize_floorplan sizes the core from the cell area and the utilization, and fills it with rows of placement sites: 8 rows, 23.5 um wide. place_pins puts the 11 I/O pins on the die edge. Then pdngen builds the power grid: thin rails along every row edge on met1, and vertical and horizontal straps on met4 and met5. tapcell adds five tap cells (dark grey) that tie the wells to the supplies. No logic cell has a position yet.

2. Placement

global_placement spreads the cells over the core so that connected cells are close, while keeping the density near the target. detailed_placement then snaps every cell into a row on a legal site with no overlaps. The blue boxes are the eight flip-flops, the green boxes are logic gates.

3. Clock Tree Synthesis

clock_tree_synthesis builds a tree of buffers from the clock pin to the eight flip-flops. For this small design it adds three clkbuf_2 cells (orange): one root buffer driving two leaf buffers, each feeding four flip-flops. After CTS, repair_timing checks setup and hold timing with the real clock and finds nothing to fix.

4. Routing

global_route plans a coarse path for every net, and detailed_route draws the actual wires on the routing tracks: here mostly met1 (horizontal, blue) and met2 (vertical, orange), with short met3 wires (green) to the pins on the left edge. Finally filler_placement fills every empty site with filler cells (light grey), so the rows are continuous.

Sign-Off and GDSII

After routing, the flow extracts the wire parasitics and checks the result:

• Timing: with propagated clocks and the extracted wire RC, the worst setup slack of the counter at 5 ns is +3.31 ns.
• Power: report_power gives about 105 uW, of which the clock network is about a third.
• IR drop: analyze_power_grid computes the voltage drop in the VDD and VSS grids.
• Antenna, DRC and LVS: checks that the layout follows the manufacturing rules and matches the netlist. For the counter, all three are clean.

The layout is written as DEF, converted to GDSII with KLayout by merging in the cell layouts, and the GDSII is what goes to the foundry. The GDSII Out and Tapeout article covers the last step in detail.

Running It in ChipVerify Lab

The example is the counter from this article. Synthesize it, then run Place and Route with the default settings. The layout viewer shows the final layout; the report has a section for each step: area and floorplan, CTS, timing, power, IR drop, antenna, DRC and LVS. The LVS section compares the layout with the netlist, as explained in Layout Versus Schematic (LVS).

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