Project: Place and Route a UART Transmitter

This project takes a complete design, a 115200-baud UART transmitter, through Place and Route in the lab and reads every part of the result: the floorplan, the clock tree, the timing at several clock periods, the reset network and the physical checks. It also shows a failure that a real design can hit on its first run, a constant tied to a flip-flop input, and two ways to fix it. The UART is the same design whose timing is analysed in the STA tutorial's UART project, with one small change for physical design.

8 min read | Intermediate

What You'll Learn

• Run a complete design through Place and Route and read each section of the result
• Find the limit of the clock period from the timing report
• Recognize a constant net that needs a tie cell, and fix it
• Read the reset network's timing: high fanout and recovery checks

The Design

The transmitter sends one byte as a start bit, eight data bits and a stop bit, at 868 clock cycles per bit for 115200 baud from a 100 MHz clock. It has 27 flip-flops: a two-stage baud divider (5 + 5 bits), a bit counter (4), a shift register (8), the active, tx and tick registers, and a two-flop reset synchronizer that asserts reset immediately and releases it on a clock edge:

always @(posedge clk or negedge rst_n) begin
  if (!rst_n) begin
    rs1 <= 1'b0;
    rs2 <= 1'b0;
  end
  else begin
    rs1 <= rst_n;   // samples the released reset
    rs2 <= rs1;
  end
end
wire rst_s = rs2;   // drives the asynchronous reset of every other flip-flop

In the STA tutorial's version, the first flip-flop samples a constant, rs1 <= 1'b1. Logically both are the same: whenever the flip-flop is out of reset, rst_n is 1. The next section shows what the constant means for Place and Route.

A Constant Needs a Tie Cell

With the original rs1 <= 1'b1, a synthesis script that only maps the logic connects the flip-flop's D input straight to logic 1, which appears in the netlist as .D(1'b1). Place and Route then runs through placement and CTS, and detailed routing stops:

[ERROR DRT-0305] Net one_ of signal type POWER is not routable by TritonRoute. Move to special nets.

The constant became a net called one_ with no driver cell, marked as a power net, which the signal router does not route. A real design needs a tie cell for every constant: a small cell whose output is permanently high or low, here sky130_fd_sc_hd__conb_1. There are three places to fix it:

• In synthesis: hilomap -singleton -hicell sky130_fd_sc_hd__conb_1 HI -locell sky130_fd_sc_hd__conb_1 LO maps every constant to a tie cell. The lab's synthesis does this, so the original version gets one conb_1 driving the D pin from its HI output, and routes with +7.10 ns of slack at 10 ns.
• In Place and Route: insert_tiecells sky130_fd_sc_hd__conb_1/HI -prefix TIE_HI_ before global placement does the same on a netlist that still has constants.
• In the RTL: avoid the constant, as in the version above, which the lab example uses.

Constants are common in real designs: unused enables, fixed configuration bits, tied-off inputs of a macro. Checking the netlist for 1'b0 and 1'b1 on cell pins before Place and Route saves a failed run.

The Run at 10 ns

Synthesize the example and run Place and Route with a 10 ns clock and the default utilization. The log and report show:

• The 27 clock sinks are exactly the 27 flip-flops. With so few, CTS builds a root buffer and two leaf buffers, and the clock reaches the flip-flops after about 0.31 ns, with no measurable skew.
• At 10 ns the worst path starts at the input start, which the flow assumes arrives 2 ns (20 % of the period) after the clock edge. Even so, the design has 70 % of the clock period to spare: a UART does very little work per cycle.

The log has no errors. Its warnings are about the input files, for example LEF statements that are obsolete in newer LEF versions, not about the design.

Finding the Clock Limit

Run Place and Route again with shorter clock periods:

At 3 ns the worst path runs between two registers through a nand2_1, a nor3_1, a nor2_1 and an a22o_1: the baud divider's compare logic. The nor3_1 stage alone takes 0.74 ns; a three-input NOR with series PMOS transistors is slow to pull high. At 2 ns, repair upsized two cells on that path, and the worst path is now a neighbour through the same divider logic:

   0.311 ^ _177_/CLK (sky130_fd_sc_hd__dfrtp_1)
   0.841 v _177_/Q (sky130_fd_sc_hd__dfrtp_1)
   1.510 ^ _099_/Y (sky130_fd_sc_hd__nor2b_1)
   1.814 v _108_/Y (sky130_fd_sc_hd__nor2_1)
   2.065 v _142_/X (sky130_fd_sc_hd__a22o_1)
   2.065 v _166_/D (sky130_fd_sc_hd__dfrtp_1)
           2.217   data required time
           0.151   slack (MET)

The nor2b_1 stage takes 0.67 ns, again a NOR pulling high, here into 0.04 pF of load. The worst hold-type check is a removal check on the reset (next section). It stays at +0.41 ns at 10 and 3 ns, because hold checks between registers do not depend on the clock period. At 2 ns the worst one starts at the rst_n input instead, whose assumed arrival, 20 % of the period, shrinks with the period.

The Reset Network

The synchronizer's second flip-flop drives the asynchronous reset pins of the other 25 flip-flops. That shows in two places:

• A slow clock-to-Q. In the 2 ns run, that flip-flop's output took 1.01 ns to rise, against 0.53 ns for the flip-flop in the worst data path, because it drives 25 reset pins and their wires.
• A recovery check. The release of an asynchronous reset must happen a recovery time before the clock edge, like a setup check. The timer reports these paths in their own group, asynchronous: at 2 ns the reset path met recovery with +0.997 ns of slack.

Recovery and removal checks are explained in the STA tutorial's article on recovery and removal checks. In larger designs the synchronized reset is buffered as a tree, like a small clock tree, so that it reaches all flip-flops in time.

Running It in ChipVerify Lab

Open the example below, synthesize it and run Place and Route at 10 ns. Find each row of the first table in the log and the report, and open the layout to see the 27 flip-flops and the three clock buffers. Then repeat at 3 ns and 2 ns and compare the worst paths. Then change the synchronizer back to the original rs1 <= 1'b1, synthesize again and find the conb_1 tie cell in the netlist.

Common Mistakes