A floorplan mistake rarely shows up where it was made. A core that is too small passes the floorplan step and fails placement; a macro facing the wrong way places fine and wrecks routing; a power strap offset off the grid stops the power grid generator with a cryptic message. This article collects the checks to run on a floorplan before moving on, and the real error messages OpenROAD gives when something is wrong, from runs made while writing this chapter.
8 min read | Intermediate
What You'll Learn
- Check a floorplan before placement: size, shape, pins, macros, blockages and power
- Recognize common OpenROAD floorplan errors and what causes them
- Tell harmless warnings from real problems
- Use a checklist to review a floorplan
A Complete Floorplan
This is the SRAM wrapper from Macro Placement right after floorplanning, before any standard cell is placed: the die and core, the macro with its 5 um halo (no rows around it), the rows with their tap cells, the I/O pins, and the power grid with met1 rails and met4/met5 straps running over the macro. Everything after this point builds on it.
The Checklist
| Check | What to look for |
|---|---|
| Size | Core area against cell area: start at 50-70 % utilization for logic, leave room for the clock tree and timing repair. A blockage or a macro halo raises the effective utilization. |
| Shape | Aspect ratio from the chip floorplan; enough edge length for the pins. |
| Pins | Pins on the edges facing the blocks they connect to; buses grouped and in order; no edge overcrowded. |
| Macros | Placed and fixed; pins facing the logic; halos; channels wide enough; macro power connected. |
| Rows | Rows cut under macros; no slivers of rows too short to hold cells. |
| Power | Rails on every row, straps covering the core, vias between layers, straps on the manufacturing grid, macros connected. |
| Tap cells | Inserted at the required spacing (14 um in the lab's flow), none inside blockages. |
Quick Check
Q: A floorplan passes every step up to placement. Why review it at all, instead of waiting for placement and routing to report problems?
Show Answer
Placement and routing take much longer than the floorplan, and their errors point at symptoms (congestion, long wires, failing timing) rather than the cause. A wrong macro orientation, for example, never causes an error, just a worse design. Fixing the floorplan first is cheaper.
Errors and Warnings You Will Meet
IFP-0028: core snapped (harmless)
[WARNING IFP-0028] Core area lower left (10.000, 10.000) snapped to (10.120, 10.880).
The core was moved to the site and row grid. Expected on every run; see Core Margin, Rows and Tracks.
GPL-0301: the core is too full
[ERROR GPL-0301] Utilization 106.180 % exceeds 100%.
The multiplier with a floorplan sized for 95 %. Global placement adds tap cells and padding for pin density, and the cells no longer fit. Lower the utilization or enlarge the die.
PDN-0185: no room for the straps
[ERROR PDN-0185] Insufficient width (26.22 um) to add straps on layer met4 in grid "grid" with total strap width 15.2 um and offset 13.6 um.
A power grid with a 27 um strap pitch on a 26 um core. Small cores need smaller pitches, or the grid must be defined relative to the core size.
PDN-0191: off the manufacturing grid
[ERROR PDN-0191] Offset of 3.2780 um does not fit the manufacturing grid of 0.0050 um.
A computed strap offset of 3.278 um is not a multiple of 5 nm. Round every coordinate you compute to the grid.
DPL-0004 and DPL-0033: cells outside rows
[WARNING DPL-0004] Placed in rows check failed (42). TAP_TAPCELL_ROW_18_106 ... [ERROR DPL-0033] detailed placement checks failed.
Tap cells were left inside a placement blockage. The final placement check counts every instance that is not in a legal row position. Remove cells from blocked regions, or create the blockage before the cells are inserted.
DRT-0305: an undriven constant
[ERROR DRT-0305] Net one_ of signal type POWER is not routable by TritonRoute. Move to special nets.
This one shows up during routing, but its cause is in the netlist: an input tied to a constant without a tie cell. Synthesis must map constants to tie-high and tie-low cells (hilomap to sky130_fd_sc_hd__conb_1).
Quick Check
Q: A design passes the floorplan but routing fails with DRT-0305 on a net called zero_. Where do you fix it?
Show Answer
In synthesis: the netlist has a constant 0 driving a pin directly. Add tie-cell mapping so a conb_1 cell drives it, then re-run place and route.
Running It in ChipVerify Lab
Run Place and Route on the multiplier and read the start of the OpenROAD log: the IFP messages describe the floorplan (utilization, rows, die and core), the PDN messages the power grid, and the TAP message the number of tap cells. Then look at the floorplan in the layout viewer before checking anything else.
Common Mistakes
Mistake #1: Ignoring warnings because the run finished
A finished run can still carry a bad floorplan. Read the warnings from the floorplan, pin and power steps, and know which ones are harmless.
Mistake #2: Fixing floorplan problems late
Every later step depends on the floorplan. Moving a macro after routing means redoing placement, clock tree and routing; check it before placement.
Practice Exercise
Challenge: Review Your Floorplan
Run Place and Route on the multiplier at 40 % utilization and go through the checklist with the log and the layout viewer: core and die size, utilization, rows and sites, number of tap cells, pin positions and the power grid. What would you change before a real tapeout?
Hint
The IFP, PPL, PDN and TAP messages at the start of the log hold most of the numbers.
Solution
The core is 155.0 x 152.3 um in a 175.5 um die, 56 rows of 337 sites, 319 tap cells and 44 % final utilization. The tool put all pins on one edge. Before a tapeout you would constrain the pins to match the surrounding blocks, and you could raise the utilization towards 60-70 %, where the sweep in the utilization sweep gave shorter wires and better timing.
Open the ready-made example in the lab, synthesize it and run Place and Route.
Summary
- Review size, shape, pins, macros, rows, power and tap cells before placement.
- IFP-0028 (core snapped) is harmless; GPL-0301 means the core is too full.
- PDN-0185 and PDN-0191 come from straps that do not fit the core or the manufacturing grid.
- DPL-0004/0033 flag cells outside legal rows; DRT-0305 points to a missing tie cell in the netlist.