Standard Cells, Rows and Sites

Standard cells are the building blocks of a digital layout: small, pre-designed layouts of gates and flip-flops that all share one height. Because they share a height, they can be lined up in rows like books on a shelf, with power and ground running along the top and bottom of every row. This article explains standard cells, placement sites and rows using the sky130 high-density library, and shows how rows alternate so that neighbouring rows share a power rail.

7 min read | Beginner

What You'll Learn

• Describe what a standard cell is and what all cells in a library have in common
• Explain placement sites and why cell widths are whole numbers of sites
• Read a ROW statement in a DEF file
• Explain why rows alternate orientation and share power rails

Standard Cells

A standard cell library holds a few hundred cells: inverters, NAND and NOR gates, AND-OR-INVERT gates, multiplexers, adders, flip-flops and latches, each in several drive strengths. The sky130 high-density library, sky130_fd_sc_hd, has 437 cells in its LEF. The suffix is the drive strength: inv_1 is the smallest inverter, inv_16 drives sixteen times the current.

All cells in the library follow the same template:

• Same height: 2.72 um for every sky130_fd_sc_hd cell, eight times the 0.34 um met1 track pitch. Libraries are often described by their height in tracks; taller cells have more room for transistors and are faster but larger.
• Width in whole sites: the site of this library, unithd, is 0.46 um wide. An inv_1 is 3 sites (1.38 um), an and3_1 5 sites (2.30 um), a dfxtp_1 flip-flop 16 sites (7.36 um).
• Power on the edges: the power pin VPWR runs along the top edge on met1, the ground pin VGND along the bottom edge. When cells are placed side by side, these rails join into one continuous wire.
• Well connections: in the Liberty and netlist views, sky130 cells also have VPB and VNB pins for the n-well and p-well (the transistor bodies). The cells do not tap their wells to the supplies themselves; separate tap cells do that. The LEF abstract used for placement leaves these two pins out.

Sites and Rows

A site is the smallest legal placement unit: one site wide and one cell high. A row is a line of sites across the core. The floorplan step creates the rows, and the placer may only put a cell so that it starts on a site boundary inside a row. In DEF, a row looks like this:

ROW ROW_0 unithd 10120 10880 N DO 57 BY 1 STEP 460 0 ;
ROW ROW_1 unithd 10120 13600 FS DO 57 BY 1 STEP 460 0 ;

Row 0 starts at (10.12 um, 10.88 um), has 57 sites of type unithd, one site every 0.46 um, so it is 26.22 um long. Row 1 starts 2.72 um higher, exactly one cell height.

This is the placed counter, zoomed in. Every cell sits in a row; the flip-flops (blue) take 16 sites, the gates (green) 3 to 8. The thin red and blue bands are the met1 rails along the row edges, and the dark grey cells are tap cells.

Why Rows Alternate

Look at the orientation in the DEF: row 0 is N (north, upright), row 1 is FS (flipped south, mirrored upside down). Flipping every other row means that the bottom edge of row 1 has the same supply as the top edge of row 0. In the counter, row 0 has VGND at the bottom and VPWR at the top; row 1, flipped, has VPWR at the bottom, sharing the VPWR rail with row 0, and VGND at the top, sharing it with row 2.

Sharing rails saves area: one rail serves two rows. It also means a cell placed in a flipped row is mirrored, which the placer handles automatically: a cell in an FS row gets orientation FS, like flip-flop _47_ in the counter: PLACED ( 12880 13600 ) FS.

Physical-Only Cells

Some cells in the library have no logic function and exist only for the layout:

• Tap cells (tapvpwrvgnd_1, 1 site): connect the wells to VPWR and VGND, at regular distances, to prevent latch-up.
• Filler cells (fill_1 to fill_8): fill empty sites so the wells and rails are continuous.
• Decap cells (decap_3 and up): small capacitors between VPWR and VGND that steady the local supply.
• Diodes (diode_2): protect gates from the antenna effect during manufacturing.

They are covered in Tap Cells, Endcaps, Latch-Up and Decaps and The Antenna Effect.

Running It in ChipVerify Lab

Run Place and Route on the counter and open the layout viewer. Zoom in on the rows and find a flip-flop, a gate, a tap cell and the fillers between them. The Area and Floorplan section of the report gives the core size and the utilization.

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