Detailed Routing and DRC-Clean Routes

Detailed routing turns the global router's plan into real metal. Every wire gets an exact track, every layer change gets a via, and every shape must satisfy the foundry's design rules: minimum width, minimum spacing, minimum area, via enclosure. OpenROAD's detailed router, TritonRoute, does this in a first routing pass followed by repair passes that rip up and reroute the wires around each violation. This article follows those passes on the 16x16 multiplier at four utilizations and explains the violation types it reports.

7 min read | Intermediate

What You'll Learn

• List the steps of detailed routing, from pin access to the final pass
• Read the violation table printed after each pass
• Explain why dense designs need more passes and much more run time
• Tell the difference between a clean route and a DRC-clean layout

The Steps of Detailed Routing

The lab's flow runs a single command, detailed_route, but the log shows several steps inside it:

• Pin access. For each distinct cell placement (cell type, orientation and position relative to the tracks), the router finds the points where a via can land on each pin without breaking a rule. The multiplier has 82 such unique instances. Pin access matters because the li1 pins in sky130 cells are small and close together.
• Guide processing. The 8,261 route guides from global routing are read and cleaned up. Each net may only be routed inside its guides, with a small margin.
• Track assignment. Long wire segments in each guide are assigned to tracks, so that parallel wires do not start on top of each other.
• Detailed routing passes. The router splits the die into small regions and routes every net in each region with a maze search, then repeats over the whole die with repair passes until no violations remain or it reaches its iteration limit.

The First Pass and Its Violations

The first pass, called the 0th optimization iteration in the log, routes every net quickly and allows violations. At 44 % core utilization it ended with:

[INFO DRT-0195] Start 0th optimization iteration.
[INFO DRT-0199]   Number of violations = 427.
Viol/Layer         li1   mcon   met1   met2
Cut Spacing          0      4      0      0
Metal Spacing        0      0     99     15
Recheck              1      0     24     10
Short                0      0    231     43

• Short: two different nets touch on the same layer. Most of them are on met1, where routes come up from the pins and the power rails also run.
• Metal Spacing: two shapes of different nets are closer than the minimum spacing for that layer and width.
• Cut Spacing: two vias (cuts) are too close; here on mcon, the li1-to-met1 cut.
• Recheck: places the router has changed and will verify again in the next pass, not confirmed errors.

Other types appear in other designs: minimum area (a metal piece too small, often a short stub around a via), minimum step, and end-of-line spacing.

Each repair pass reroutes the wires in the regions that hold violations, using different region boundaries and higher costs for shapes that caused violations before. The 44 % run went from 427 to 306 to 191 to 0 violations in four passes.

Dense Designs: More Passes, Much More Time

The same multiplier was routed at four core utilizations, in die sizes from 175 um down to 127 um, as in Global Routing and Congestion, with a placement target density of 0.95 and no capacity reserve in global routing. The chart shows the violations left after each pass:

Every run ended with zero violations, but the effort was very different:

• First-pass violations roughly triple once the core is dense: more pins per area, fewer free tracks, more nets competing for the same spots.
• The tail is slow. The 75 % run was stuck at 1,019 violations for one pass, and once it was down to 101 it took four more passes to clear them. The last violations sit in the tightest spots and each one may need many reroutes.
• Run time depends on the placement, not only on utilization. The order of the dense runs is not monotonic: the 75 % run took longest because of where its hardest spots ended up.

The placement matters more than the table suggests. At 75 % the placer's minimum feasible density was 0.79, but it was allowed to pack cells up to 0.95, so it built tight clusters next to empty space. The same die placed at density 0.83, with a 0.5 capacity reserve in global routing and the per-layer wire RC values of OpenROAD-flow-scripts, routed clean in 5 passes and 3 minutes, against 10 passes and 52 minutes. Much of the run time came from an overpacked placement, not from the utilization itself, which is why Debugging Congestion starts with the placement.

Leaving routing margin still matters in real projects. A block that routes clean but takes ten times longer slows down every iteration of the design.

Clean Routing Is Not DRC Sign-Off

Zero violations at the end of detailed_route means the router found no violations of the rules it checks. Two caveats:

• The router reads the design rules from the technology LEF, which does not contain every rule of the foundry's rule deck. In the lab's runs it even warns that it skips some of the rules it does read:

  [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon
  

• The router checks only the routing layers it uses, not the cells' internal layers or fill.

So the final layout still goes through a full DRC run on the GDSII with the foundry deck. In sky130 flows this is done with KLayout or Magic, described in Design Rule Checking (DRC).

When violations do remain, the lab's flow writes them to drc_violations.rpt, with the rule, the layer and the location of each one.

Running It in ChipVerify Lab

Run Place and Route on the multiplier and find the detailed routing section of the log: the pin access step, the number of guides, and the violation count after each pass. The multiplier at 40 % went from 255 to 105, 107 and 0 violations in four passes; a second, short detailed route follows when the post-route antenna repair has added diodes. Then open the DRC section of the report (KLayout), which is the sign-off check on the GDSII.

The lab's flow places with a density just above the real core utilization and keeps the 0.5 reserve, the settings of the 3-minute run above, and it shows: the multiplier at 70 % and 75 % utilization finished the whole lab run in 4 and 5 minutes. Free jobs stop after 5 minutes and PRO jobs after 30; with PRO, a limit on the detailed routing passes makes a run stop early and report the violations left.

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