A physical sign-off checklist is the list of checks a block must pass before it is declared done, each with the command that runs it and the result that counts as a pass. The individual checks are explained in their own articles. This checklist puts them in order, adds the pass criteria, and records the lessons from the runs in this tutorial: settings that changed a verdict, checks that passed on a broken layout, and warnings that turned out to matter.
8 min read | Intermediate
What You'll Learn
- Go through the sign-off checks in the order they depend on each other
- State a pass criterion for each check
- Recognize settings that change a check's verdict
- Avoid the traps found in this tutorial's runs
How to Use the Checklist
Run the checks on the final design, after the last ECO, in the order below: later checks assume the earlier ones passed. A check counts only if it ran on the right input (the streamed GDSII for DRC and LVS, extracted parasitics for timing) with the settings recorded. Each row links to the article that explains it.
1. Inputs and Constraints
| Check | How | Pass |
|---|---|---|
| Every clock and I/O path constrained | check_setup -verbose | No unconstrained endpoints, no ports missing input or output delays |
| Libraries and corners as intended | Log of read_liberty, corner list | Every sign-off corner loaded |
| Estimates calibrated | set_layer_rc values in the script | Per-layer values correlated with extraction |
On the multiplier, check_setup reported 64 unconstrained endpoints: with only a clock defined, none of its I/O paths had ever been timed, while every timing report looked clean. See Antenna, ERC and Density Checks. Uncalibrated RC values understated long nets by 45 % and made the repair steps leave an undersized driver, as measured in Parasitics After Routing.
2. Placement and Routing
| Check | How | Pass |
|---|---|---|
| Placement legal | check_placement -verbose | No overlaps, every cell in a row, on a site |
| Global route has margin | Congestion report, GRT-0101 iterations, the reserve in the routing resources table | Zero overflow with a capacity reserve, few extra iterations |
| Detailed route clean | Last DRT-0199 line, drc_violations.rpt | Zero violations |
| Antenna | check_antennas on the final routes | Zero net and pin violations |
The global router's verdict depends on its capacity reserve: with none, an overpacked two-layer placement showed zero overflow and then failed detailed routing for 12 hours; with a reserve of 0.5, the global router rejected it in minutes. See Debugging Congestion. Antenna repair before detailed routing missed violations that the real wires created, so the check that counts runs on the final routes, as shown in The Antenna Effect.
3. Timing
| Check | How | Pass |
|---|---|---|
| Parasitics extracted | extract_parasitics, read_spef | Timing below uses the SPEF, not an estimate |
| Setup at the slow corner | report_checks -path_delay max per corner | WNS at or above zero, with the IR drop budget in the voltage |
| Hold at the fast corner | report_checks -path_delay min per corner | WNS at or above zero, with hold uncertainty |
| Electrical limits | report_check_types -max_slew -max_capacitance | No violations |
| Clock tree | report_clock_skew, CTS report | Skew and latency within budget |
The same layout of the multiplier passed setup by 2.92 ns at the typical corner and failed by 3.87 ns at the slow one; its worst hold was at the fast corner. See Post-Route STA and Fixing Hold in Layout. A repair step that improved the estimated slack made the extracted slack slightly worse, as shown in Fixing Setup in Layout. In sky130 the fanout limit cannot trigger, because the library's fanout loads are zero, so slew and capacitance are the limits to check.
Quick Check
Q: A block meets setup at the typical corner with extracted parasitics. Which two timing checks are still missing for sign-off?
Show Answer
Setup at the slow corner, where cells are slowest and the supply lowest, and hold at the fast corner, where short paths are fastest. The multiplier passed typical by almost 3 ns and still failed at the slow corner.
4. Physical Verification
| Check | How | Pass |
|---|---|---|
| Stream-out complete | Stream-out log, via counts against the routing | No invalid-via or missing-cell warnings, counts match |
| DRC | Foundry deck on the streamed GDSII (KLayout sky130A.drc, feol, beol, offgrid) | Zero violations |
| LVS | Magic extraction and Netgen on the streamed GDSII | "Circuits match uniquely" |
| Floating nets | report_floating_nets | None |
| Density | PDK density check over 700 um windows | All layers within limits at chip level |
Three findings from these checks:
- A stream-out without the technology LEF dropped all 8,408 routing vias of the two lowest layers with only two warnings. See GDSII Out and Tapeout.
- A VDD-to-VSS short passed DRC with zero violations; only LVS found it. See Design Rule Checking.
- The first LVS runs on a correct layout failed on setup: floating body pins in the netlist, escaped bus names and different device names. See Layout Versus Schematic.
5. Power
| Check | How | Pass |
|---|---|---|
| Grid connected | check_power_grid per supply | All shapes connected, power pins present for integration |
| Static IR drop | analyze_power_grid at the high-current corner | Below the budget, typically 2 to 3 % of the supply |
| EM | analyze_power_grid -enable_em, per wire and via | Every element below its limit, vias included |
The multiplier's grid was fully connected but had no power pins, so the analysis assumed supply bumps over the block. Its IR drop of 0.02 % is a block-level budget check, not the chip's drop. See Power Sign-Off: IR Drop and EM.
Quick Check
Q: DRC is clean and every timing check passes. Which single check on this list would catch a short between two signal nets made by a hand edit?
Show Answer
LVS. Overlapping shapes on the same layer merge without breaking a geometry rule, and timing may still pass. LVS compares the layout's connectivity with the netlist and reports the merged net.
Settings That Change a Verdict
Several checks in this tutorial gave a different answer depending on a setting, not on the design. Record these settings with every sign-off result:
| Setting | Effect seen in this tutorial |
|---|---|
| Per-layer RC values for estimates | Estimated slack -0.92 ns (uncalibrated) or -1.53 ns (calibrated) for the same design |
| Global routing layer adjustment | Zero overflow with none; rejection with 0.5, even of a routable placement |
| Placement target density | Two-layer route of a 78 % core: 12 hours without a clean route at 0.95; clean in under 3 hours at 0.82 |
| Order of constraints | Layer limits set after placement made routability-driven placement do nothing |
| Input and output delays | Missing: 64 endpoints never timed |
| Supply model in IR analysis | Assumed bumps over the block instead of the real supply path |
A sign-off result without its settings cannot be reproduced or compared. Keeping the scripts and logs with the results is part of the checklist.
Running It in ChipVerify Lab
Run Place and Route on the multiplier and go through the list with the lab's report: the checks section with check_setup and the floating nets, the CTS, clock and timing sections with extracted parasitics and hold repair, the IR drop, antenna, DRC, LVS and density sections. With PRO, the multi-corner option adds the slow and fast corners. What the lab cannot check for a block is what this checklist leaves to the chip: density windows, the chip-level power grid and the merged chip file.
Common Mistakes
Mistake #1: Running checks on intermediate data
Timing on estimates, DRC on the database or LVS before the last ECO do not count. Run the checks on the final, streamed and extracted design.
Mistake #2: Ignoring warnings because the check passed
The dropped vias, the unconstrained endpoints and the missing power pins all showed up as warnings, not errors.
Mistake #3: Comparing results made with different settings
The same design gave different slack, congestion and routability verdicts under different settings. Keep the settings with the result.
Practice Exercise
Challenge: Order the Checks
After an ECO that resized 9 cells, a team wants to re-sign the block. Put these steps in order and say which can be skipped: (a) LVS on the GDSII, (b) extraction, (c) stream-out, (d) DRC on the GDSII, (e) setup and hold at all corners, (f) detailed routing of the changed connections, (g) antenna check.
Hint
Each check needs the output of an earlier step. An ECO changes the layout.
Solution
(f) detailed routing, (g) antenna check on the new routes, (b) extraction, (e) timing at all corners, (c) stream-out, (d) DRC and (a) LVS on the streamed file. None can be skipped: the ECO changed cells and wires, so every check that depends on them must run again.
Open the ready-made example in the lab, synthesize it and run Place and Route.
Summary
- Sign-off runs constraints, placement and routing, timing, physical verification and power checks on the final design, in that order.
- Each check has a pass criterion and must run on the right input: extracted parasitics for timing, the streamed GDSII for DRC and LVS.
- In this tutorial, clean-looking results hid unconstrained I/O paths, a DRC-clean power short and a stream-out that dropped every via of the two lowest routing layers.
- Settings changed verdicts, so they belong with every sign-off result.
