This is the first article in a hands-on series that walks you through ChipVerify Lab feature by feature, using a single running example so each new tool builds on work you've already done rather than starting from scratch each time.
4 min read | Beginner Level
What You'll Learn
- What this series covers, end to end — design, verify, synthesize, analyze, and physically implement a chip
- The design you'll build: a 4-bit universal shift register with internal hierarchy
- How PRO-only features are marked throughout the series, so you always know what's available on your plan
- Where to start: Chapter 1
What You'll Build
Across this series you'll design a 4-bit universal shift register: a small register that can parallel-load a 4-bit value, then shift it left or right one bit per clock edge based on a dir input. It's built from four identical shift_reg_bit instances wired together under one top-level module, shift_register_4bit — small enough to synthesize and place-and-route in seconds, but structured with real hierarchy, so the schematic and hierarchy-navigation chapters later in the series have something genuine to explore.
module shift_register_4bit (
input wire clk,
input wire rst,
input wire load, // parallel-load parallel_in (overrides dir)
input wire dir, // 0 = shift right, 1 = shift left
input wire [3:0] parallel_in,
output wire [3:0] parallel_out
// serial in/out ports omitted here — full listing in Chapter 1
);
How This Series Is Organized
Every chapter is a short, self-contained article that hands you off to the next one — you don't need to remember where you left off, and ChipVerify Lab's own chapter menu tracks your place.
| Chapter | What You'll Do |
|---|---|
| 1. Your First Project | Create a project, tour the editor, add the RTL |
| 2. Simulate & Verify | Run a testbench, read the waveform |
| 3. Lint & Synthesize | Clean up warnings, synthesize to gates |
| 4. Explore the Schematic | Read the schematic, navigate into hierarchy |
| 5. Analyze PPA & Timing | Read area/power, run full timing analysis |
| 6. Synthesizing Across Libraries | Compare PPA across standard-cell libraries |
| 7. Physical Design: PnR & DRC | Place-and-route, understand design-rule checks |
| 8. Get Help with Ask AI | Debug a run with the built-in AI assistant |
| 9. Coverage Reports | Measure and close verification coverage gaps |
| 10. Learning Sessions | Track your work across a whole project |
| 11. Wrap-up & What's Next | Recap, and where to go from here |
How PRO Callouts Work
ChipVerify Lab's FREE tier covers the full design flow — you can simulate, lint, synthesize, and even place-and-route the design in this series without upgrading. A few tools go further on PRO: full static timing analysis, synthesizing across additional standard-cell libraries, design-rule checking, and Learning Sessions. Wherever a step needs PRO, you'll see a callout like this one, so you always know what you're looking at and what upgrading adds:
Steps marked like this are PRO-only. You'll still see what they do and why they matter — you just won't be able to run them yourself until you upgrade.
Where Is This Used?
The design → verify → synthesize → analyze → implement flow you're about to walk through isn't a simplified teaching version — it's the same sequence of steps used on real ASIC and FPGA projects, from student capstone designs to production chips. What changes at larger scale is the size of the design and the depth of each step, not the flow itself.
Before You Start
You'll need a ChipVerify Lab account (FREE or PRO — this series works on either) and about 45 minutes total if you go through every chapter in one sitting. Each chapter also stands alone if you'd rather come back to it later.
Click here to get started with ChipVerify Lab !
Summary
In this introduction, you learned:
- This series takes one design through the full ChipVerify Lab flow: design, verify, synthesize, analyze, and implement
- The running example is a 4-bit universal shift register with real internal hierarchy
- PRO-only steps are called out inline with a lock badge, not hidden
- Every chapter is self-contained — jump in at Chapter 1 whenever you're ready
