TinyTapeout is a shared tapeout programme in which many small designs go onto one chip, each in a tile of a fixed size. Designing for a tile turns the usual question around: the die is given, and the design must fit it. This project places and routes two designs in the lab's TinyTapeout mode, a UART transmitter that fits easily and a 16x16 multiplier that fits only at 91 % utilization, and reads what changes when the floorplan is fixed.
7 min read | Intermediate
What You'll Learn
- Explain how a fixed tile outline changes the floorplan and the flow
- Estimate whether a design fits a tile from its cell area
- Read a tile run: rows, utilization, fillers and timing
- Decide between a larger tile and a smaller design
The Tile
In TinyTapeout mode (PRO), the lab replaces its utilization-based floorplan with a fixed outline:
| Tile | Die | Core | Cell limit in the lab |
|---|---|---|---|
| 1x1 | 160 x 100 um | 140 x 80 um | 1,500 cells |
| 1x2 | 160 x 200 um | 140 x 180 um | 3,000 cells |
| 2x2 | 320 x 200 um | 300 x 180 um | 6,000 cells |
The floorplan command becomes initialize_floorplan -die_area {0 0 160 100} -core_area {10 10 150 90}: the core is given, and the utilization follows from the design instead of the other way round. The lab rejects a design whose synthesized cell count exceeds the tile's limit before Place and Route starts. The real programme also fixes where each tile's pins and power connections are; the lab's mode reproduces the outline and the cell limits. Its power grid stops at met4: the met1 rails are joined by met4 straps, and met5 is left to the chip, as a real tile's grid is.
A Design That Fits: the UART
The UART transmitter from Project: Place and Route a UART Transmitter in the 1x1 tile at 10 ns:
| UART at 10 ns | Normal floorplan | 1x1 tile |
|---|---|---|
| Rows x sites | 17 x 104 | 29 x 304 |
| Tap cells | 28 | 155 |
| Utilization | 55 % | 13 % |
| Fillers | 191 | 1,272 |
| Worst setup slack | +7.04 ns | +6.87 ns |
| Antenna violations | 0 | 0 |
- The tile's core holds 29 rows of 304 sites, 139.8 x 78.9 um. The UART's 1,161 um2 of cells cover only 13 % of it.
- The empty space still needs tap cells in every row and fillers in every gap: five to seven times more taps and fillers than the UART's own floorplan.
- Timing barely changes. The cells cluster where the placer puts them, and the clock tree has the same three buffers.
A small design in a fixed tile wastes area but is easy to close. For a shared tapeout that is fine: the tile is paid for either way.
A Design That Barely Fits: the Multiplier
The 16x16 multiplier has 1,267 cells after synthesis, within the 1x1 limit of 1,500, and 9,668 um2 of cell area. The 1x1 core is 139.8 x 78.9 = 11,030 um2 of rows, so the cells alone would fill 88 % of it before tap cells and repair buffers.
Run in the 1x1 tile, the placer first refused the flow's target density, already at the flow's maximum of 0.95:
[INFO GPL-0019] Utilization: 95.024 % [WARNING GPL-0302] Target density 0.9500 is too low for the available free area. [INFO GPL-0023] Placement target density: 0.9600
With cells, tap cells and the pin-density allowance, 95 % of the free area was needed, so the placer raised the target to 0.96 by itself. The run then completed: 92 % final utilization, 410 fillers and no antenna violations left. But it took 4 minutes 8 seconds, against 2 minutes 6 seconds in the 1x2 tile and under a minute for the UART, and it missed the 10 ns clock by 1.53 ns. The repair step had found no violation in its estimate; in the crowded core the routes of the critical path detoured, and its nets carry about a quarter more capacitance than in the 1x2 tile. A design at 92 % utilization routes slowly, misses timing that a roomier floorplan meets, and leaves no room for a later fix.
In the 1x2 tile, with a core of 65 rows of 304 sites, the multiplier is comfortable:
| Multiplier at 10 ns, 1x2 tile | Result |
|---|---|
| Rows x sites | 65 x 304 (176.8 x 139.8 um) |
| Tap cells | 335 |
| Clock tree | 64 sinks, 9 buffers |
| Design area and utilization | 10,424 um2, 42 % |
| Worst setup slack | +0.16 ns |
| Antenna violations | 4 after global routing, 0 after repair |
The cell limit is a first filter, not a guarantee. Whether a design fits a tile depends on its area, the share of the core it may use while still routing, and its pins.
Quick Check
Q: The multiplier passes the 1x1 tile's cell limit. Why is that not enough to know that it fits?
Show Answer
The limit counts cells, not area. The multiplier's cells are large on average and would cover 88 % of the 1x1 core before tap cells and repair, far above the utilization at which a design routes comfortably. Cell area against core area, with room for taps, buffers and routing, is the real test.
Fitting a Design to a Tile
- Estimate first. Cell area from synthesis divided by the core area gives the starting utilization; aim for 50 to 70 % so that taps, repair buffers and routing have room.
- Choose the tile. A larger tile costs more in a shared tapeout but saves a hard closure.
- Shrink the design. A smaller architecture, such as a serial multiplier instead of an array, or fewer bits, can turn a 1x2 design into a 1x1 design.
- Check the pins. In the real programme every tile has the same pin positions; a design with more I/O than the tile provides must multiplex them.
Quick Check
Q: A design synthesizes to 6,000 um2 of cells. Which lab tile would you start with, and at what utilization?
Show Answer
The 1x1 core holds about 11,030 um2 of rows, so 6,000 um2 would be about 54 % before taps and repair, a reasonable starting point. If the design has many pins or a congested datapath, the 1x2 tile, at about 24 %, is the safe choice.
Running It in ChipVerify Lab
With PRO, open the UART example below, synthesize it, enable TinyTapeout mode with the 1x1 tile and run Place and Route at 10 ns. Compare the rows, taps, fillers and utilization with a normal run. Then try the multiplier example (pd-mult16) in the 1x2 tile and in the 1x1 tile, and compare the run time and the worst slack.
Common Mistakes
Mistake #1: Trusting the cell limit as a fit check
The limit counts cells. Compare the cell area with the core area and leave room for taps, buffers and routing.
Mistake #2: Choosing the smallest tile for a dense datapath
The multiplier filled 92 % of the 1x1 tile, needed twice as long as in the 1x2 tile and missed timing by 1.5 ns, while the 1x2 tile closed. A larger tile or a smaller design is cheaper than a hard closure.
Mistake #3: Ignoring the empty space
Unused tile area still needs taps and fillers, and still counts for density. A tiny design in a large tile should be placed and filled like any other.
Practice Exercise
Challenge: Which Tile?
Three designs have these synthesized cell areas: (a) an 8-bit counter, 280 um2; (b) the 32-bit pipelined adder, 4,085 um2; (c) two 16x16 multipliers, 19,336 um2. Using the core areas of 11,030 um2 (1x1), 24,700 um2 (1x2) and about 53,800 um2 (2x2), which tile would you choose for each, aiming for at most 60 % utilization from cells?
Hint
Divide the cell area by each core area and take the smallest tile under 60 %.
Solution
(a) 280 / 11,030 = 2.5 %: 1x1, mostly empty. (b) 4,085 / 11,030 = 37 %: 1x1. (c) 19,336 / 24,700 = 78 % is too much for 1x2; 19,336 / 53,800 = 36 %: 2x2. The counter would also pass on cell count; the two multipliers would need the 2x2 tile's 6,000-cell limit as well, since they have about 2,500 cells.
Open the ready-made example in the lab, synthesize it and run Place and Route.
Summary
- TinyTapeout mode fixes the die and core to the tile outline; the utilization follows from the design.
- The UART used 13 % of a 1x1 tile and closed timing as easily as in its own floorplan, with five times more taps and fillers.
- The multiplier passes the 1x1 cell limit and even routed there at 92 % utilization, but in twice the time and 1.5 ns short of 10 ns; in the 1x2 tile it routed in 2 minutes at 42 % with +0.16 ns slack.
- Fit a design to a tile by cell area, not cell count, and leave room for taps, buffers and routing.