I/O Pin Placement

Every input and output of a block needs a pin on the edge of its die, and where those pins go matters more than it first seems. The placer pulls the cells connected to a pin towards it, so the pins shape the whole placement, and in a chip the block's pins must line up with the blocks around it. This article explains how OpenROAD places pins, how to constrain them to edges, and what pin placement did to the wire length of the 16x16 multiplier.

7 min read | Beginner to Intermediate

What You'll Learn

• Explain how the pin placer chooses pin positions and layers
• Constrain pins to die edges with set_io_pin_constraint
• See how pin positions change placement and wire length
• List the rules for good pin placement in a real chip

Pins in the Lab's Flow

The lab's flow places pins with one command, after the floorplan and the power grid:

place_pins -hor_layers met3 -ver_layers met2

Pins on the left and right edges are horizontal pins and use met3; pins on the top and bottom edges are vertical pins and use met2. Each pin sits on a routing track of its layer, with at least one track between neighbours. Without constraints, the placer is free to choose any edge and slot, and it tries to keep the wires from the pins to the cells short. It reports an estimate:

[INFO PPL-0012] I/O nets HPWL: 6674.20 um.

HPWL, the half-perimeter wire length, is a quick estimate of wire length: for each net, half the perimeter of the box that contains all its pins. Here it is summed over the nets that connect to I/O pins.

What Pin Placement Does to the Layout

Three runs of the multiplier, identical except for the pin constraints:

In the default run the pin placer put the pins together on the bottom edge, and the input and output registers (blue) gathered there. With inputs on one side and outputs on the other, the registers split into two groups at opposite edges and the logic spreads between them. The pin-only estimate is the same for both constrained runs, but after placement and routing the second one needs 2.1 mm (7.6 %) more wire. The estimate looks only at the pins; the real cost depends on how the logic inside lines up with them.

Constraining Pins

OpenROAD constrains pins before place_pins:

set_io_pin_constraint -direction input  -region left:*
set_io_pin_constraint -direction output -region right:*
place_pins -hor_layers met3 -ver_layers met2

-region left:* means anywhere on the left edge; a range such as bottom:20-80 limits pins to part of an edge. Constraints can also select pins by name (-pin_names {a* b*}), keep a bus together and in order (-group -order), or fix a single pin exactly with place_pin. In the lab, these lines go into the OpenROAD script, which PRO users can edit.

Pin Placement in a Real Chip

• Follow the chip floorplan: a block's pins face the blocks they connect to. The top-level floorplan decides which edge each interface uses.
• Keep buses together and in order: bit 0 next to bit 1, so the wires do not cross each other between blocks.
• Mind the clock: the clock pin is usually placed so the clock tree can start near the middle of the block.
• Leave room: many pins on one short edge cause congestion in the margin; spread them or use more layers.

Running It in ChipVerify Lab

Run Place and Route on the multiplier and find the pins in the layout viewer: which edge did the pin placer choose? With PRO, add the two set_io_pin_constraint lines before place_pins in the OpenROAD script and compare the placement.

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