GDSII Out and Tapeout

GDSII out, or stream-out, turns the routed DEF into the GDSII file that goes to the foundry, by writing every wire and via as polygons and merging in the full layout of every cell. Tapeout is the moment that file, checked and complete, is handed over for manufacturing. The name dates from the days when the finished layout was written to reels of magnetic tape and the tape itself was shipped to the mask maker. This article runs the stream-out of the routed 16x16 multiplier, shows how a stream-out can quietly lose thousands of vias, inventories what the final file contains, and lists what a block still needs before it can become part of a chip.

7 min read | Intermediate

What You'll Learn

• Describe the steps of a KLayout stream-out in an OpenROAD flow
• Check a stream-out for missing cells and dropped vias
• Read the contents of a final GDSII file
• List what tapeout adds beyond a clean block

The Stream-Out Steps

The layer basics are in GDSII and Layout Layers. In practice the lab's flow, like OpenROAD-flow-scripts, streams out in two steps with KLayout:

python3 generate_klayout_tech.py --template sky130hd.lyt --output klayout.lyt \
        --lef-files sky130_fd_sc_hd.tlef sky130_fd_sc_hd_merged.lef --reference-dir output
klayout -b -r def2stream.py -rd tech_file=klayout.lyt -rd in_def=layout.def -rd design_name=mult16 \
        -rd in_files=sky130_fd_sc_hd.gds -rd out_file=layout.gds

• The technology file. KLayout's .lyt file holds the layer map and the list of LEF files to read. The first step writes a copy that points to the actual technology and cell LEFs of the run.
• The stream-out. def2stream.py reads the DEF with those LEFs, draws every wire and via, places a reference to each cell, and copies the cell layouts from the library GDSII into the output.

On the multiplier it printed:

[INFO] All LEF cells have matching GDS/OAS cells
[INFO] No orphan cells in the final layout

The first line says every cell used in the DEF has a layout in the library GDSII. The second says the output contains no cell without a parent, such as a stray cell from the library file that the design does not use.

A Stream-Out That Drops Vias

The routes in the DEF use vias defined in the technology LEF, such as L1M1_PR_MR from li1 to met1 and M1M2_PR from met1 to met2. If KLayout does not read that LEF, it does not know them. The same DEF was streamed out once more with the template .lyt, which lists no technology LEF:

Warning: Invalid via name: L1M1_PR_MR (line=24070, cell=, file=layout.def)
Warning: Invalid via name: M1M2_PR (line=24070, cell=, file=layout.def)
[INFO] All LEF cells have matching GDS/OAS cells
[INFO] No orphan cells in the final layout

The stream-out finished, with the same two INFO lines as before, and wrote a GDSII file. Counting the cut shapes in both files:

4,339 mcon cuts and 4,069 via cuts were missing, exactly the numbers of L1M1_PR_MR and M1M2_PR vias the router placed. The cuts that remained belong to the cells and to vias defined in the DEF itself. Every pin connection of the design was open, and the only signs were two warnings and a smaller file. DRC would pass most of it, since missing cuts break no width or spacing rule; LVS would fail with opens everywhere.

The lesson is general: a stream-out that ends without an error is not proof of a complete GDSII. Read its warnings, compare the via counts with the routing report, and always run LVS on the streamed file, not on the database.

What the Final GDSII Contains

The correct file for the multiplier, read back with KLayout:

• 63 cells: the top cell mult16 and 62 cells it uses, standard cells and the via cells of the routing.
• 13,544 instances in the top cell: 4,339 li1-to-met1 vias, 4,069 met1-to-met2 vias, 2,429 filler cells, and the logic, tap and clock cells.
• Shapes on 34 layer and datatype pairs: from the n-well (64/20) and diffusion (65/20) inside the cells up to met5 (72/20) in the power grid, plus pin and label layers.
• 65 pin shapes on met2 (69/16) with 65 labels (69/5): the 64 data ports and the clock, which the pin placer put on the bottom edge on vertical met2.
• One placement boundary (235/4) marking the block's outline.

The DEF of the same design was 1.31 MB, the GDSII 1.59 MB: the GDSII stores every routed wire as a polygon and every cell's full layout once.

From Clean Block to Tapeout

A block that passes DRC, LVS, antenna and timing is ready to be integrated, not yet to be manufactured. A chip for tapeout also needs:

• An I/O ring of pad cells that connect the core to the package, with ESD protection; see Building the Pad Ring and ESD Protection for Physical Designers.
• Power pins on every block, so the chip-level grid can connect to it. The multiplier's grid is complete inside, but as Antenna, ERC and Density Checks showed, its database has no power pins; Hierarchical Physical Design shows how its straps become pins in the block abstract.
• Chip-level fill and density. Density is checked over 700 um windows across the whole chip.
• A seal ring around the die, which protects the circuit from cracks and moisture at the sawn edge.
• Final checks on the merged chip GDSII: DRC, LVS, antenna and density on the file that is actually sent, not on its parts.

Shared tapeouts, where many small designs go on one multi-project wafer, provide the I/O ring, seal ring and chip-level checks, and each designer delivers a block of a fixed size with fixed pin positions. TinyTapeout is such a programme; the lab's TinyTapeout mode uses its tile of 160 x 100 um.

Running It in ChipVerify Lab

Run Place and Route on the multiplier and download the GDSII from the report. Open it in KLayout with the sky130 layer properties and look for the met2 pins on the bottom edge and the met5 power straps. The lab counts the vias that the stream-out could not write, the Invalid via name messages of the trap described above, and reports them. With PRO, the power pins option turns the met5 straps into VDD and VSS pins of the block, as a chip-level grid needs, and the TinyTapeout mode places and routes the design inside a TinyTapeout tile outline, the shape a shared tapeout expects.

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