Multi-voltage implementation builds a chip whose parts run at different supply voltages, or can be switched off, to save power. Each part is a power domain with its own supply, and every signal that crosses between domains needs a special cell: a level shifter when the voltages differ, an isolation cell when the source can be off. This article explains what multi-voltage design asks of the physical implementation, using the actual low-power cells in the sky130 hd library and the commands OpenROAD provides for power domains.
7 min read | Intermediate
What You'll Learn
- Explain why designs use several voltages and power shutoff
- Describe level shifters, isolation cells and always-on cells from their library data
- List what multi-voltage adds to floorplan, power grid, placement and routing
- Recognize the power intent commands in OpenROAD
Why Several Voltages
Dynamic power grows with the square of the supply voltage, and leakage grows with it too. Running a block at a lower voltage saves power at the cost of speed, and switching it off when idle removes both its dynamic power and its leakage. A chip may therefore run its fast processor core at a high voltage, its peripherals at a lower one, and switch off whole blocks between bursts of activity.
The intent, which domains exist, which supplies feed them, which states they can be in, and which cells guard their boundaries, is written in UPF (Unified Power Format), covered in the UPF tutorial. This article is about what that intent means for the layout.
The Special Cells in sky130
The sky130 hd library contains a set of cells whose names start with lpflow_, for low-power flows. Their Liberty descriptions show what each one does.
Level shifter
cell ("sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1")
area : 35.0336
is_level_shifter : "true";
level_shifter_type : "HL_LH";
input_voltage_range(1.2, 2.1);
output_voltage_range(1.2, 2.1);
pg_pin ("VPWRIN") ... pin ("A") related_power_pin : "VPWRIN";
pg_pin ("VPWR") ... pin ("X") related_power_pin : "VPWR"; function : "(A)";
A level shifter passes a signal from one supply to another. This one has two supply pins: its input side runs on VPWRIN, the voltage of the domain the signal comes from, and its output side on VPWR, the voltage of the receiving domain. It shifts in both directions (HL_LH, high to low and low to high) for supplies from 1.2 to 2.1 V. With 35 um2 it is larger than a flip-flop, which is one reason the number of signals crossing between voltage domains is kept small.
Isolation cells
cell ("sky130_fd_sc_hd__lpflow_inputiso0p_1") area : 7.5072
is_isolation_cell : "true";
pin ("SLEEP") isolation_cell_enable_pin : "true";
pin ("X") function : "(!SLEEP&A)";
When a domain is switched off, its outputs float at undefined levels. A floating input in a powered domain can make its gate draw current or pass garbage into logic that is still running. An isolation cell sits on the signal, powered by the receiving domain, and clamps it to a known value while the source is off: with SLEEP high, this cell's output is 0. The library also has versions that clamp to 1 and a latching version that holds the last value.
Always-on cells
cell ("sky130_fd_sc_hd__lpflow_clkbufkapwr_1") area : 3.7536
always_on : "true";
pg_pin ("KAPWR") pg_type : "backup_power";
pin ("A") related_power_pin : "KAPWR";
Some signals must keep working inside a domain that is switched off: the control that wakes it up, a clock to retention registers. Always-on cells run on a separate supply, here KAPWR (keep-alive power), so they stay alive while the domain's main supply VPWR is off. The library has always-on clock buffers, inverters and decaps.
The lab's synthesis keeps all these cells out of ordinary logic with -dont_use sky130_fd_sc_*__lpflow*. That is correct: they are inserted by the power intent at domain boundaries, not chosen by the logic mapper.
Quick Check
Q: A signal goes from a domain that can be switched off, running at 1.2 V, to an always-on domain at 1.8 V. Which special cells does it need?
Show Answer
Both: a level shifter, because the voltages differ, and isolation, because the source can be off and its output would float. In practice they are often combined, as in level shifters with an isolation enable, and placed in the receiving, powered domain.
What It Asks of the Layout
- Voltage areas in the floorplan. Each domain gets a region of the core, and its cells must be placed inside it. Cells of different supplies cannot share a row, since the row's rails carry one supply.
- A power grid per domain. Each region gets its own grid for its own supply. A switched domain also needs power switch cells between the always-on supply and its switched rail, controlled by a sleep signal, with enough of them to limit the voltage drop when on and the inrush current when turning on.
- Boundary cells in the right place. Level shifters and isolation cells are placed at the domain boundary, in the domain that powers them, and their second supply pin (
VPWRINorKAPWR) must be routed to the right net. - Secondary power routing. Always-on cells inside a switched domain need the always-on supply routed to them as a signal-like power net, separate from the domain's rails.
- Timing and checks per state. Each combination of domain voltages is analysed with the right library voltages, and LVS and power-aware checks verify that every crossing has its level shifter or isolation cell.
Power Intent in OpenROAD
The OpenROAD build used in this tutorial accepts power intent in UPF and has commands for domains and their regions:
read_upf -file design.upf
create_power_domain [-elements elements] name
set_domain_area domain_name -area {llx lly urx ury}
set_level_shifter ... -domain domain -source source -sink sink ... name
set_domain_area turns a domain into a placement region. The power grid generator takes power switch options, define_pdn_grid ... -power_switch_cell -power_control, for switched domains, described in Power Gating: Switches, Retention and Rush Current. Domains must be hierarchical instances of the netlist, so a multi-voltage design keeps its hierarchy through synthesis instead of being flattened. A complete multi-voltage flow also needs Liberty files characterized at each domain voltage and an LVS setup that understands the extra supply pins; the UPF tutorial's article on UPF physical implementation describes the steps.
Quick Check
Q: Why can a level shifter not be placed anywhere in the core, like an ordinary buffer?
Show Answer
It needs two supplies: the source domain's voltage for its input side and the receiving domain's voltage for its output. It must sit where both are available, at the boundary between the domains, with its VPWRIN pin connected to the source supply. A placement deep inside one domain would leave one supply unreachable.
Running It in ChipVerify Lab
At the time of writing the lab's flow has a single 1.8 V domain: one supply pair, one power grid, and the lpflow_ cells excluded from synthesis. The library data above can be read in the Liberty files that come with the PDK, and the multiplier's power report shows the dynamic and leakage power that multi-voltage techniques reduce.
Common Mistakes
Mistake #1: Letting synthesis use special cells as ordinary logic
Level shifters, isolation and always-on cells have extra supply pins and must only appear where the power intent places them. Exclude them from logic mapping.
Mistake #2: Forgetting isolation on signals from a switched domain
A level shifter alone does not clamp a signal whose source is off. Every output of a switchable domain into a powered domain needs isolation.
Mistake #3: Mixing supplies in one row
A row's rails carry one supply. Cells of another domain belong in their own region with their own rails.
Practice Exercise
Challenge: Counting the Cost of Boundaries
A switchable 1.2 V domain has 40 outputs going to an always-on 1.8 V domain and 25 inputs coming from it. Each output needs a level shifter (35.0 um2) and an isolation cell (7.5 um2); each input needs a level shifter. What is the boundary cell area? How does it compare with the multiplier's 10,000 um2 of logic?
Hint
Add the level shifters for both directions and the isolation cells for the outputs.
Solution
Level shifters: (40 + 25) x 35.0 = 2,275 um2. Isolation: 40 x 7.5 = 300 um2. Total about 2,575 um2, a quarter of the multiplier's logic area. Domain boundaries are not free, which is why designers choose them where few signals cross.
Open the ready-made example in the lab, synthesize it and run Place and Route.
Summary
- Multi-voltage designs run domains at different voltages or switch them off to save dynamic and leakage power.
- sky130 hd provides a level shifter (35 um2, two supplies), isolation cells with a SLEEP enable and always-on cells on a keep-alive supply.
- The layout needs voltage areas, a grid per domain with power switches, boundary cells at the edges and secondary power routing.
- OpenROAD reads UPF and has commands for power domains, domain areas and level shifter strategies; the lab's flow uses a single domain.
