Why Clock Trees: Skew, Latency and Transition

Every flip-flop in a synchronous design needs the same clock edge at nearly the same moment. Before clock tree synthesis, timing analysis pretends that happens for free: the clock is ideal, with zero delay and zero skew to every flip-flop. In the layout, the clock pin is one point at the edge of the die and the flip-flops are spread over the core. A clock tree is the network of buffers and wires that carries the edge from that pin to every clock input with controlled delay, skew and edge rate. This article explains those three quantities and what CTS achieved for the 16x16 multiplier.

7 min read | Intermediate

What You'll Learn

• Define clock latency, skew and transition
• Explain why one wire cannot drive all clock pins
• Describe how skew affects setup and hold checks
• Read the clock latency and skew reports after CTS

The Ideal Clock and the Real One

Up to placement, the clock is ideal. The timing engine treats the edge as arriving at every flip-flop at time zero, with an instant rise. That is a good assumption early on, because the clock network does not exist yet, and an unbuffered clock net would give meaningless numbers.

In the multiplier, one clk port drives the CLK pins of 64 flip-flops placed across an area of about 100 x 60 um. Driving that load from one point with one wire has three problems:

• The total load is far more than any single cell can drive with a sharp edge. A data net with 64 loads in the same library reached a 2.27 ns transition, against a 1.5 ns limit, as shown in Design Repair.
• Flip-flops close to the driver would see the edge earlier than flip-flops at the far end of the wire.
• A slow edge increases the delay and the short-circuit power of every clock input it drives.

Clock tree synthesis (CTS) solves all three by building a tree of clock buffers, each driving a small group of flip-flops, with paths of nearly equal delay from the root to every leaf.

Latency, Skew and Transition

• Latency (insertion delay) is the time from the clock source to a flip-flop's clock pin. In a tree it is the sum of the buffer and wire delays along the path.
• Skew is the difference in latency between two flip-flops. For a timing path, the skew that matters is between its launch and capture flip-flops. The tool also reports the largest skew over all related pairs.
• Transition (slew) is the rise or fall time of the clock edge at a pin. Clock nets usually get a tighter transition target than data nets, because the clock edge rate sets the flip-flop's clock-to-Q delay and its setup and hold times.

Latency on its own is mostly harmless: if every flip-flop sees the same 0.31 ns delay, the launch and capture edges move together and cancel in each timing check. It matters for paths that leave or enter the block, and when two parts of the clock tree are affected differently by voltage or temperature. Skew is what directly changes the timing of internal paths.

Skew in the Setup and Hold Checks

Take a path from a launch flip-flop FF1 to a capture flip-flop FF2, with clock latencies L1 and L2. The skew is L2 - L1.

• Setup: the data launched at the first edge must arrive before the next edge at FF2. With positive skew, the capture edge comes later, so the path gets that much more time. Negative skew takes time away.
• Hold: the new data launched at an edge must not reach FF2 before FF2 has captured the old data at the same edge. With positive skew, FF2 captures later, so the new data has more chance to overtake it. Positive skew makes hold harder.

So skew moves time between setup and hold: whatever skew helps one check costs the other. Zero skew is the neutral choice, and it is what a CTS tool aims for by default. Skew, Useful Skew and Hold After CTS looks at the exceptions.

What CTS Achieved for the Multiplier

The lab's flow runs clock_tree_synthesis after placement. For the multiplier it built a tree with one root buffer and eight leaf buffers, all clkbuf_16. With the clock switched from ideal to propagated, the latency report of the routed design shows the result:

report_clock_latency

Clock clk
rise -> rise
    min     max
   0.00    0.00 source latency
   0.32         network latency _2432_/CLK
           0.33 network latency _2414_/CLK
---------------
   0.32    0.33 latency
           0.01 skew

The shortest clock path takes 0.32 ns and the longest 0.33 ns, so the skew is 0.01 ns. Each clock path goes through exactly two buffers: the root buffer and one leaf buffer, about 0.16 ns each.

The Clock's Share of Power

The clock net switches twice every cycle, on every flip-flop, whether or not the data changes. That makes the clock network one of the largest consumers of dynamic power. The final power reports of three designs from this chapter, with the default activity the tool assumes for data signals:

The "clock" group counts the clock buffers and their wires. The flip-flops' own clock pins are counted in the "sequential" group, so the real cost of the clock is higher still. In designs dominated by registers, the clock tree is often the largest single item in the power budget, which is why clock gating matters.

Running It in ChipVerify Lab

Run Place and Route on the multiplier and find the CTS section of the log. Note the number of clock buffers the tool created, the number of buffers on each clock path, and the sink count of the clock net. The CTS section of the report has the same numbers, and the clock section the latency and skew after routing. Then compare the worst slack before CTS with the final worst slack after routing.

Common Mistakes