Power and Ground Pads: How Many and Where

All the current a chip uses enters through its supply pads or bumps and leaves through its ground pads. Each of those connections has inductance and resistance, so the number of supply pads, and where they sit, decides how much the supply bounces when outputs switch or the core wakes up. Most high-performance chips devote about half their pins to power and ground. This article shows where that number comes from: the ground bounce of switching outputs, the current steps of the core, the separation of noisy and quiet supplies, and the placement rules that follow.

8 min read | Intermediate

What You'll Learn

• Calculate ground bounce from simultaneously switching outputs
• Estimate how many ground pads an output group needs
• Explain why I/O and core supplies are kept separate
• Place supply pads to keep noise and IR drop low

Inductance in the Supply Path

A bond wire is not just a resistor. Its inductance is about 1 nH per millimetre, while a flip-chip solder bump is on the order of 100 pH. A changing current through an inductance creates a voltage across it:

V = L x dI/dt

When the current through a ground pad rises quickly, the chip's internal ground rises above the board's ground by this voltage. Every signal referenced to that ground shifts with it. This is ground bounce, and its counterpart on the supply side is supply droop. Inductors in parallel divide their inductance, so more pads mean less bounce.

Simultaneously Switching Outputs

Outputs are the biggest source of fast current steps. Take a 16-bit bus switching together, with these assumptions:

• each output drives 10 pF on the board, with a 3.3 V swing and a 1 ns edge;
• the ground connections are bond wires 3 mm long, so 3 nH each;
• the current rises from zero to its full value within one edge time.

Each output then carries C x dV/dt = 10 pF x 3.3 V / 1 ns = 33 mA during the edge, 528 mA for all sixteen. That current rises in about 1 ns, so dI/dt is 0.528 A/ns:

With one ground pad, the internal ground jumps by almost half the I/O supply, which could flip the inputs of other pads. To keep the bounce under 10 % of 3.3 V, the group needs five ground pads, roughly one for every three outputs. The same calculation with 100 pH flip-chip bumps gives 0.05 V for a single bump, one of the reasons flip-chip packages handle wide, fast buses better.

The calculation also shows the other levers. Doubling the edge time to 2 ns halves the current per output and spreads it over twice the time, cutting dI/dt by four: 0.40 V with a single pad. That is what the slow mode of the sky130 GPIO cell, from I/O Cells: Drivers, Receivers and Level Shifting, is for. Lower loads, lower swings and outputs that do not all switch at once help in the same way.

Core Current Steps

The core produces current steps too, when a block wakes up, a clock gate opens, or a burst of activity starts. Consider a chip whose current jumps from 20 A to 60 A in one 1 ns cycle; with 20 pH of supply inductance the noise would be 0.8 V without on-chip bypass capacitance.

A small chip shows the same effect at a smaller scale. If the core current steps from 0.1 A to 0.5 A in 5 ns through 3 nH bond wires, the droop is 3 nH x 0.4 A / 5 ns = 0.24 V with one supply pad, 0.12 V with two, 0.06 V with four. Decoupling capacitance on the die, from Tap Cells, Endcaps, Latch-Up and Decaps, supplies the first nanoseconds of such a step locally, and the supply pads and package capacitors supply the rest.

Dirty and Quiet Supplies

Because output switching is so noisy, it is good practice to separate the supply that feeds the output drivers from the core supply. The I/O drivers get their own pads and buses, often called the "dirty" supply, and the core and any analog circuits get their own "quiet" supplies. The separation is essential when the I/O runs at a different voltage than the core, and useful even when it does not.

The sky130 I/O cells reflect this: they have separate I/O supplies (VDDIO, VSSIO), quiet I/O references (VDDIO_Q, VSSIO_Q), analog supplies (VDDA, VSSA) and core supplies (VCCD, VSSD). Caravel brings in each of these through its own pads: vddio at 3.3 V for the I/O and ESD, vccd at 1.8 V for the management core, vdda at 3.3 V for analog, and separate 1.8 V and 3.3 V supplies for each of the two user areas.

How Many Pads, and Where

The pad count for each supply comes from several limits, and the largest one wins:

• Noise. The ground bounce and droop calculations above, for each output group and for the core.
• Current per pad. Each pad, bond wire or bump has a maximum current, from electromigration in its metal and heating in the wire. The I/O library and the package documentation give the values.
• IR drop. The resistance from the pad through the ring bus and the core grid to the farthest cell, analysed as in IR Drop: Static and Dynamic with the real pad positions as sources.
• ESD. Clamped supply pads must be close enough to every signal pad, as in ESD Protection for Physical Designers.

Placement rules follow from the same physics:

• Interleave supply and ground pads with output groups, so each group's current returns through nearby pads. Wide buses are interdigitated with many power and ground pins.
• Put core supply pads near the blocks that draw the most current.
• Place a supply pad and its ground pad next to each other, so the current loop through the package is small.
• Spread pads around all sides, which helps IR drop, ESD and noise at once.
• Keep analog supply pads away from fast digital outputs.

Caravel's Supply Pads

Caravel's padframe, read in Building the Pad Ring, has 18 clamped supply pads for 44 GPIO cells, about one supply pad for every 2.4 signal pads, spread over all four sides. In its package, several ground pads share balls, and the documentation's pinout lists the grounds vssio, vssa and vssd together on four balls. Package decisions like this one are the subject of Chip-Package Co-Design.

Running It in ChipVerify Lab

The lab's IR drop analysis, described in Power Sign-Off: IR Drop and EM, assumes supply bumps over the block or feeds the grid from its strap pins with PRO. It does not model pad inductance at the time of writing. The noise numbers in this article are calculations with the stated assumptions and typical inductance values.

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