What Is Post-Silicon Validation?

Post-silicon validation is the work of checking that a chip behaves as intended once real silicon exists. It starts when the first chips come back from the fab and continues until the decision to begin mass production.

Before tapeout, every check runs on a model of the design: a simulator, an emulator or an FPGA prototype. After tapeout, the chip itself is the thing under test, running real software at full speed, at real voltages and temperatures, on real boards. This article explains what post-silicon validation covers, why it is needed even after years of pre-silicon verification, and how it differs from the manufacturing test that every shipped chip goes through.

7 min read | Beginner

What You'll Learn

• Define post-silicon validation and where it sits in a chip's life
• Explain why bugs survive pre-silicon verification and appear in silicon
• List the main activities of post-silicon validation
• Distinguish post-silicon validation from manufacturing test

Testing a Model, Then Testing the Chip

All the verification a team does before tapeout, simulation, formal checks, emulation, works on models of the design. Post-silicon validation uses a fabricated, preproduction chip as the validation vehicle instead. Its goal is to make sure the silicon works under actual operating conditions while executing real software, and to find the errors that pre-silicon validation missed.

Seen from the test side, chip tests fall into three kinds:

• Logic verification, run before tapeout to check that the design performs its intended function.
• Silicon debug, run on the first batch of chips from the fab to confirm that the chip works as intended and to chase down any differences. These tests can be much more extensive than pre-silicon ones, because the chip runs at full speed in a real system: a new processor can be put on a prototype board and asked to boot an operating system.
• Manufacturing test, run on every chip that is shipped, to check that each one was built without defects.

Post-silicon validation is the middle category, grown into a discipline of its own. It is about the design: does this design, built in silicon, do what it should?

Manufacturing test is about each part: was this particular die built correctly? This tutorial covers the first; manufacturing test belongs to a separate test tutorial.

Why Bugs Reach Silicon

If simulation and formal verification are so thorough, why do chips still have bugs when they come back? Several reasons combine:

• Speed. RTL simulation runs roughly a billion times slower than the target clock. Booting an operating system takes seconds on silicon and would take years in an RTL simulator, so pre-silicon tests are short. Long, realistic workloads first run on the chip.
• Scale. A system-on-chip combines many blocks, firmware and software. Most pre-silicon tests exercise one block or a few interactions; the chip exercises all of them together, with timing interleavings no testbench thought of.
• Physics. A simulator does not model supply noise, temperature, process variation or analog behaviour in full. Some failures appear only at a certain voltage, frequency and temperature.
• The system around the chip. Most failures of first-time silicon come from functionality problems: the chip does exactly what the simulator said it would, but that is not what the rest of the system expects. A specification misread, a protocol corner handled differently by another chip, a board that behaves differently from the model.

What Post-Silicon Validation Covers

The main activities each have a chapter of their own in this tutorial:

• Power-on and bring-up. Getting the first chips to power up, run a clock, come out of reset and accept a debugger connection. See The Post-Silicon Timeline.
• Functional validation. Running focused, random and self-checking tests, then real software, to find logic bugs.
• Compatibility validation. Checking the chip with the operating systems, peripherals and applications it will meet in products. For a large system-on-chip this commonly covers over a dozen operating systems, more than a hundred peripherals and hundreds of applications.
• Electrical validation. Checking I/O, power delivery, clocks and analog blocks across voltage, temperature and many parts, to show the chip has margin under worst-case conditions.
• Speed-path validation. Finding the paths that limit the maximum frequency in silicon, which are not always the ones static timing analysis predicted.
• Debug and fixes. Finding the root cause of every failure, working around bugs so validation can continue, and deciding what the next silicon revision must fix.

Alongside these run characterization, which measures how many parts reach which speed and power, and reliability qualification, which shows the chip will last its intended life. All of it feeds one decision at the end: whether the design is ready for mass production.

The Price of a Late Bug

A classic estimate of what it costs to detect a fault at each level runs from about one to ten cents at the wafer, up to a dollar for a packaged chip, up to ten dollars on a board, up to a hundred in a system, and a hundred to a thousand dollars in the field.

The best-known example is the floating-point divider bug in an early Pentium processor, which was not corrected until more than 4 million units had shipped in 1994 and cost the company an estimated 450 million dollars.

Post-silicon validation is the last chance to find design bugs before that last, most expensive stage. That is why companies spend so much on it. Validation as a whole is estimated to take about 70 percent of the time and resources of an SoC design, and over 20 percent of a design's silicon area can be devoted to features that support silicon validation.

In Practice

A typical sequence for a new system-on-chip: the first wafers come out of the fab, a first batch of packaged parts arrives at the validation lab, and the bring-up team works on a debug board until the chip powers on reliably, which can take from a few days to a week.

Over the following weeks more teams join: functional validation runs test suites and boots software, electrical validation measures I/O and power, and debug engineers work through every failure. Bugs that cannot be worked around are fixed in a new silicon revision, which goes through the same steps more quickly. The process ends with the production release decision, described in The Post-Silicon Timeline.

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