Power sign-off checks that the power grid delivers the supply voltage to every cell with little enough loss, and that no wire or via in it will wear out from electromigration over the chip's lifetime. The two analyses, IR drop and EM, are explained in IR Drop and Electromigration. This article is about the sign-off run itself: which corner to use, what the numbers depend on, and what a static analysis leaves out, using the routed 16x16 multiplier at the typical and fast corners.
7 min read | Intermediate
What You'll Learn
- Choose the corners for IR drop and EM sign-off
- Run
analyze_power_gridwith EM output on a routed design - Explain how the supply model and switching activity shape the result
- List what static power sign-off does not cover
Which Corner?
IR drop and EM are driven by current, and the switching current is highest where cells switch fastest at the highest supply: at the fast corner, ff (1.95 V, -40 °C). Leakage is highest at high temperature instead, so designs with large leakage also check a fast corner at high temperature. The effect of the drop on timing is worst at the slow corner, ss, where the supply is already low. Sign-off therefore usually checks the grid for current at the fast corner and folds the resulting drop into the voltage of the slow timing corner, as a budget: if the grid loses at most 2 % of the supply, timing is signed off at the slow corner's voltage minus that 2 %.
The Sign-Off Run
The routed multiplier at a 10 ns clock, with the met4 and met5 straps of Building a PDN in OpenROAD and extracted signal parasitics, was analysed in two sessions, one per corner library:
read_liberty sky130_fd_sc_hd__ff_n40C_1v95.lib read_db layout.odb create_clock -name clk -period 10 [get_ports clk] set_propagated_clock [all_clocks] read_spef layout.spef report_power analyze_power_grid -net VDD -enable_em -em_outfile em_VDD.rpt analyze_power_grid -net VSS -enable_em -em_outfile em_VSS.rpt
The via resistances, which the sky130 technology LEF does not contain, were set with set_layer_rc -via before the analysis, as in the PDN article. The results:
| Multiplier, 10 ns clock | tt (1.80 V, 25 °C) | ff (1.95 V, -40 °C) |
|---|---|---|
| Total power (report_power) | 3.83 mW | 4.41 mW |
| Worst IR drop on VDD | 0.32 mV (0.02 %) | 0.34 mV (0.02 %) |
| Worst ground bounce on VSS | 0.20 mV | 0.22 mV |
| Highest current in a VDD grid segment | 0.39 mA | 0.41 mA |
The fast corner draws 15 % more power and carries 6 % more current in the worst segment. Both drops are tiny, far below the common static target of 2 to 3 %. The highest current, 0.41 mA, sits on a met5 strap 1.6 um wide, whose limit from the technology LEF is 1.6 x 10.17 = 16.3 mA: 2.5 % of it. As Electromigration showed on the same kind of grid, the single via cuts between the top layers come much closer to their limits than the wide straps, so the EM report must be read per element, vias included.
Quick Check
Q: Why is the grid checked for current at the fast corner, while timing is signed off at the slow corner?
Show Answer
The fast corner has the highest supply voltage, the fastest switching and therefore the highest current, which is what causes IR drop and electromigration. Timing suffers most at the slow corner, where cells are slowest and the voltage is lowest. The drop found at the high-current corner is then subtracted from the slow corner's supply as a safety margin for timing.
What the Numbers Depend On
The supply model
The block has no power pins, so the analysis had to assume where the current enters. It used a default bump pattern:
[INFO PSM-0073] Using bump pattern with x-pitch 140.0000um, y-pitch 140.0000um, and size 70.0000um with an reduction factor of 3x.
That models a flip-chip package with supply bumps over the block, as in Flip-Chip: Bump Maps and RDL Routing, the best case for a small design: every cell is close to a bump. If the same block were fed from the edge of a chip through a long chip-level grid, the drop at the block's edge would come on top. An IR drop result is only as good as the model of where the supply enters, so a block-level number is a budget check, and the real number comes from the chip-level analysis with the package.
The switching activity
No switching activity was given, so report_power used the timer's defaults. The currents, and with them the drop and the EM numbers, scale with activity. Sign-off power uses activity from simulation of a realistic workload (VCD or SAIF files) or a deliberately pessimistic assumption, never the defaults.
What Static Sign-Off Leaves Out
- Dynamic IR drop. The analysis above uses average currents. Right after a clock edge the current peaks at many times the average, and the local drop with it. Dynamic analysis needs the time-varying currents and the capacitance of the grid and decaps; OpenROAD's power grid analysis is static.
- Signal-wire EM. Signal wires carry current in both directions, and their limits are for RMS and peak current, not the DC limits used for the grid. They matter for long, heavily loaded nets such as clock trunks.
- Self-heating and temperature. EM limits in the LEF are given at a junction temperature of 90 °C. A hotter chip has lower limits.
Quick Check
Q: The static IR drop was 0.02 % of the supply. Does that prove the grid is strong enough?
Show Answer
Not on its own. It used average currents with default activity and assumed supply bumps right over the block. Peak currents after a clock edge, a real workload's activity and the chip-level path from the package to the block can all raise the drop. It proves that the block's own grid has plenty of margin, which is the part the block designer controls.
Running It in ChipVerify Lab
Run Place and Route on the multiplier and open the IR Drop section of the report. The lab's power grid has the met1 rails and the met4 and met5 straps described in Building a PDN in OpenROAD, and the analysis runs at the default switching activity with the same assumed bumps over the block: 0.32 mV worst drop on VDD and 0.22 mV on VSS. With PRO, the power pins option turns the met5 straps into VDD and VSS pins of the block, and the analysis then feeds the grid from those pins instead of the assumed bumps. On the multiplier the worst drops became 0.21 mV on both nets: two full-width straps feed the grid as well as the bump pattern did. The flow reports no EM check; with PRO, add -enable_em to analyze_power_grid in a custom script.
Common Mistakes
Mistake #1: Checking IR drop at the typical corner only
The fast corner carries the most current. Check the grid there and budget the drop into the slow corner's timing.
Mistake #2: Trusting a block-level drop as the chip's drop
The block-level analysis assumes where the supply enters. The chip-level grid and the package add their own drop.
Mistake #3: Signing off power with default activity
Power, IR drop and EM all scale with switching activity. Use activity from a realistic simulation or a stated pessimistic assumption.
Practice Exercise
Challenge: An IR Drop Budget
A project allows a static drop of 2 % of the supply. The slow corner library is characterized at 1.60 V. At what supply should the slow-corner timing be checked to include the budget? And if the grid were 3 times weaker than the multiplier's, with the drop at ff scaling in proportion, would the multiplier still meet the budget?
Hint
Take the 2 % of the slow corner's supply. The measured worst drop at ff was 0.34 mV.
Solution
2 % of 1.60 V is 32 mV, so timing would be checked at about 1.57 V, with a library characterized at that voltage or delays derated to it. A grid 3 times weaker gives about 3 x 0.34 = 1.0 mV of drop, still far below 32 mV. For this small block the budget is easy; it is large chips with high current and long supply paths that come close to it.
Open the ready-made example in the lab, synthesize it and run Place and Route.
Summary
- Power sign-off checks IR drop and EM at the high-current corner (ff) and budgets the drop into slow-corner timing.
- The multiplier's grid lost at most 0.34 mV on VDD at ff, and its worst strap segment carried 2.5 % of its EM limit.
- The result depends on the supply model (here assumed bumps over the block) and on switching activity (here the defaults).
- Static analysis leaves out dynamic drop, signal-wire EM and temperature effects.
