Dicing and Packaging

Dicing cuts the finished wafer into individual dies along the scribe lanes, and packaging gives each good die the connections, protection and heat path it needs to sit on a circuit board. The package is not an afterthought for physical design: whether the die is wire-bonded at its edge or flipped onto solder bumps over its whole area decides where the pads go, how power enters the chip, and how the I/O ring and the power grid are planned. This article covers thinning and dicing, the two ways of connecting a die, the common package types, and what each one asks of the layout.

7 min read | Intermediate

What You'll Learn

• Describe wafer thinning and the main dicing methods
• Explain the role of the scribe lane and the seal ring
• Compare wire bonding and flip-chip, and the packages built on each
• Connect the package choice to pads, bumps and the power grid

Thinning and Dicing

A finished 300 mm wafer is a little under 1 mm thick, much thicker than a package needs. Before dicing, the wafer is mounted face down on a protective tape and ground thinner from the back, often to a few hundred micrometres, and further for stacked or very thin packages. Thinning also helps heat leave the die.

The thinned wafer is mounted on a dicing tape stretched over a metal frame, and cut along the scribe lanes:

• Blade dicing. A thin diamond saw cuts through the wafer. It is the classic method; the cut (the kerf) and the chipping beside it need a scribe lane wide enough to contain them.
• Laser dicing. A laser ablates a groove, sometimes followed by a blade, which avoids mechanical stress on fragile low-k dielectrics.
• Stealth dicing. A laser focused inside the silicon creates a weakened layer along the lane, and stretching the tape splits the dies apart with almost no kerf, which allows narrower lanes.

The dies stay on the tape in their wafer positions, so the die-picking machine can use the wafer map from sort, described in Who Does What After Tapeout, and pick only the good ones.

The Scribe Lane and the Seal Ring

The scribe lane holds the foundry's test structures and alignment marks, all of which the saw destroys. The edge of each die is protected by the seal ring, a continuous wall of every metal and via layer, tied into the passivation, that stops cracks from the saw and moisture from creeping in sideways through the dielectric stack.

The sky130 layer tables show that the seal ring is not just a few lines of metal: there are marker layers for the seal ring area, for a "deadzone" around it used for metal stress relief checks, and for critical corners and sides where stress rules apply. Large metal shapes near the die corners are restricted because the corners take the highest stress when the package cools after assembly.

Wire Bond or Flip-Chip

Wire bonding glues the die face up onto the package and connects each pad to the package with a thin wire. Gold wires are about 25 um thick, and the pad pitch is limited by the bonding machine to about 100 to 200 um, so the pads sit in a ring around the die edge, the pad frame. Copper wire is now common for cost, and fine-pitch bonding reaches below that range, but the principle is the same: the I/O count is limited by the perimeter. A chip with many I/Os and little logic can become pad-limited, its size set by the pad ring rather than the core.

Flip-chip puts solder bumps or copper pillars on pads in the top metal over the whole die area, flips the die face down and melts the bumps onto a package substrate. Underfill epoxy fills the gap and spreads the mechanical stress. The connections are shorter, with far less inductance than bond wires, and there can be thousands of them. Power and ground can enter anywhere on the die, which makes the on-die power grid much more effective.

Common Package Types

A wafer-level chip-scale package (WLCSP) is the smallest: the package is the die plus a redistribution layer that moves the pads to a ball grid, a protective layer and the balls, all processed on the whole wafer before dicing. The sky130 PDK documentation includes WLCSP rules from two packaging providers, and its mask list has the masks for this option: a copper redistribution layer (CU1M), a polymer layer (PBO) and a second polyimide (PMM2).

2.5D packages place several dies side by side on a silicon interposer with very fine wiring; 3D stacks dies on top of each other, connected by through-silicon vias or direct bonding. Both need known good dies, because one bad die spoils the whole stack.

What the Package Asks of the Layout

• Pads or bumps. A wire-bond chip needs an I/O ring with pads, ESD protection and power pads at the edge, as listed in GDSII Out and Tapeout. A flip-chip needs a bump map, decided at floorplanning, with power and ground bumps spread over the core.
• Power entry. With edge pads, current enters at the periphery and the IR drop is worst in the centre; with bumps it enters all over. This is why IR Drop: Static and Dynamic depends on where the supply connections are assumed.
• Pin order. The order of signals around the die must suit the package and the board; reversing it later means a new floorplan.
• Stress. Keep-out rules near corners and under bumps protect fragile dielectrics during assembly and thermal cycling.

Running It in ChipVerify Lab

Run Place and Route on the multiplier and open the IR drop section of the report. The lab assumes a grid of supply bumps over the block, 70 um bumps at a 140 um pitch, because the block has no power pins of its own: in effect, a flip-chip connection. Compare the worst drop with the drop near a bump; then think about how much larger it would be if all current entered from one edge.

Common Mistakes