Fixing Hold in Layout

Fixing hold in layout means adding delay to paths that are too fast, without breaking the paths that are already too slow. Hold is first checked after clock tree synthesis, as described in Skew, Useful Skew and Hold After CTS, but it is only closed for real at the end of the flow: on the routed layout, with extracted parasitics, at the fast corner where hold is hardest. This article repairs hold on a 64-bit shift register with all three corners in view and shows what the fix costs.

7 min read | Intermediate

What You'll Learn

• Explain why hold is closed after routing and at the fast corner
• Read a fast-corner hold path with a delay cell and clock uncertainty
• Repair hold across several corners at once and measure the cost
• Describe the hold fixes that are used after routing

Why Hold Is Closed Late

A hold check compares a data path that is too short with the capture clock. Three things decide it, and all three are only final after routing:

• Clock skew. A capture clock that arrives later than the launch clock eats hold margin. The skew comes from the clock tree and its routed wires.
• The fast corner. At the ff corner (1.95 V, -40 °C) every cell switches sooner, so short data paths get shorter in time. Hold is checked there, while setup is checked at the slow corner.
• Late changes. Setup repair, ECOs and rerouting all change paths. A hold fix made too early can be undone, or a setup fix can create a new hold problem.

The fixes add delay, which costs area and can hurt setup. So hold is usually repaired after setup, and checked again after every later change.

The Shift Register Without Hold Repair

A shift register is the classic hold risk: each flip-flop feeds the next one directly, with no logic in between. The 64-bit shift register was placed and routed at a 10 ns clock with 0.5 ns of hold uncertainty, the per-layer RC values of OpenROAD-flow-scripts, and no hold repair:

Setup has almost the whole 10 ns to spare, but hold fails. Estimate and extraction agree within 0.01 ns: the nets are short, and hold here is decided by the flip-flop's clock-to-Q delay, the skew and the uncertainty, not by the wires.

Repairing Hold at All Corners

The same design was run again with the three corners defined from the start (see Post-Route STA) and repair_timing -hold after the setup repair. With several corners, the repair works on the worst hold slack of any corner:

[INFO RSZ-0046] Found 63 endpoints with hold violations.
Iteration | Resized | Buffers | Cloned Gates |   Area   |   WNS   |   TNS   | Endpoint
        0 |       0 |       0 |            0 |    +0.0% |  -0.296 | -18.009 | _15_/D
    final |       0 |      63 |            0 |   +42.2% |   0.072 |   0.000 | _15_/D
[INFO RSZ-0032] Inserted 63 hold buffers.

Before the repair, the worst hold slack was -0.296 ns at the fast corner, worse than the -0.17 ns at typical, and 63 of the 64 flip-flops failed. The repair inserted one delay cell, sky130_fd_sc_hd__dlygate4sd3_1, in front of each failing flip-flop, for 42.2 % more cell area. After routing and extraction, at each corner:

The repair stopped as soon as the worst corner passed: ff ends at +0.07 ns, with no margin to spare, while the slower corners got more hold slack than they needed. Setup lost about half a nanosecond at typical (from +9.57 to +9.02 ns), which a shift register can easily afford.

Reading the Fast-Corner Hold Path

The worst hold path after the repair, at the ff corner:

     Cap     Slew    Delay     Time   Description
                     0.000    0.000   clock clk (rise edge)
   0.034    0.083    0.116    0.116 ^ clkbuf_0_clk/X (sky130_fd_sc_hd__clkbuf_4)
   0.024    0.063    0.126    0.242 ^ clkbuf_3_6__f_clk/X (sky130_fd_sc_hd__clkbuf_4)
            0.063    0.000    0.243 ^ _14_/CLK (sky130_fd_sc_hd__dfxtp_1)
   0.002    0.026    0.190    0.433 ^ _14_/Q (sky130_fd_sc_hd__dfxtp_1)
   0.003    0.037    0.370    0.803 ^ hold1/X (sky130_fd_sc_hd__dlygate4sd3_1)
            0.037    0.000    0.803 ^ _15_/D (sky130_fd_sc_hd__dfxtp_1)
                              0.803   data arrival time

                     0.000    0.000   clock clk (rise edge)
   0.027    0.069    0.131    0.246 ^ clkbuf_3_7__f_clk/X (sky130_fd_sc_hd__clkbuf_4)
            0.069    0.001    0.248 ^ _15_/CLK (sky130_fd_sc_hd__dfxtp_1)
                     0.500    0.748   clock uncertainty
                    -0.017    0.731   library hold time
                              0.731   data required time
                              0.072   slack (MET)

• The two flip-flops sit on different leaf buffers. The capture clock arrives 5 ps later than the launch clock, a small skew against hold.
• The flip-flop's clock-to-Q delay is only 0.19 ns at ff. Without the delay cell, the data would arrive at 0.433 ns against 0.731 ns required.
• The delay cell adds 0.37 ns. A dlygate4sd3 is built for delay: it has slow internal stages, so it gives much more delay per area than a chain of buffers.
• The 0.5 ns of hold uncertainty is added on the required side. It stands for clock jitter, on-chip variation (see On-Chip Variation, Derates and Sign-Off Corners) and margin, and here it is most of what the delay cell had to cover.

Hold Fixes After Routing

• Delay cells in front of the capture flip-flop, as above. The standard fix, placed close to the endpoint so the setup paths through other branches are not affected.
• Downsizing a cell on the short path, if the same cell is not on a setup-critical path.
• Longer routes. A detour adds wire delay without a cell, useful in an ECO where there is no room to insert one.
• Clock adjustments. Delaying the launch clock or advancing the capture clock helps hold on that path but changes setup on every other path through those flip-flops, so it is a careful, local change.

Every hold fix must be checked at the slow corner for setup. A path that is short at ff can be part of a longer path at ss through the same cells.

Running It in ChipVerify Lab

Run Place and Route on a shift register and look at the hold section of the STA report. The lab's flow runs repair_timing -hold after the setup repair, at the corner chosen for synthesis. With PRO, set a hold uncertainty of 0.5 ns and the multi-corner option in the panel: on the 64-bit shift register the hold repair inserted 63 delay cells at the typical corner, and the multi-corner report of the routed layout then showed +0.57 ns of hold slack at ff and +6.68 ns of setup slack at ss. Compare the cell area with a run without the uncertainty.

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