GDSII and Layout Layers

GDSII is the file format a chip is delivered in. It holds the complete layout as polygons on numbered layers, organised into a hierarchy of cells, with every transistor of every standard cell included. The mask shop turns each layer into a photomask. Place and route works with LEF and DEF, and the very last step merges the full cell layouts into the routed design and writes GDSII. This article explains how GDSII describes a layout, how sky130 numbers its layers, and how the lab produces the GDSII of a design.

7 min read | Beginner to Intermediate

What You'll Learn

• Explain how GDSII stores a layout: cells, references and polygons
• Read sky130 layer and datatype numbers
• Recognize the base layers of a standard cell: well, diffusion, poly, contacts, li1, met1
• Describe how DEF and the cell GDS are merged into the final GDSII

How GDSII Describes a Layout

A GDSII file (also called a stream file) is binary and contains a library of cells, called structures. Each cell holds:

• Boundaries and paths: polygons and wires, each on a layer number and a datatype number.
• References to other cells, placed at a position with a rotation or mirror. A single reference can also be an array.
• Text labels, used for pin names.

The top cell of a chip references the standard cells, which may reference smaller cells in turn. Each standard cell is stored once and referenced thousands of times, which keeps the file small. GDSII has no notion of nets, timing or even which polygons are transistors: it is pure geometry. The newer OASIS format stores the same information more compactly.

Layers and Datatypes

Every polygon has a layer number and a datatype. The PDK's layer map gives them meaning. For sky130:

The pattern is regular: each metal layer has its own number, datatype 20 is the drawn shape, 44 the via or contact above it, 16 the pin shape and 5 the text label. There are many more layers for implants, high-voltage devices, resistors and identification markers; the display colours and names live in the KLayout layer properties file (sky130hd.lyp).

Inside a Flip-Flop

This is sky130_fd_sc_hd__dfxtp_1 from the library GDS, showing the base layers up to met1. The n-well covers the top half, where the PMOS transistors sit; the NMOS transistors are in the bottom half. Each red poly line crossing a green diffusion is a transistor. Yellow licon contacts connect diffusion and poly to the orange li1, and grey mcon cuts connect li1 to the met1 power rails. The cell has 14 poly shapes, 50 contacts and 16 li1 shapes. The LEF abstract of this cell shows only its outline, its five pins (D, CLK, Q, VPWR, VGND) and the li1 obstructions.

From DEF to GDSII

The lab's flow writes the routed design as DEF, then KLayout builds the GDSII:

• it reads the technology LEF and cell LEF, and the DEF with every placed cell and routed wire;
• it writes the wires, vias and power grid of the DEF as polygons on the right layers, using the layer map;
• it merges the library GDS (sky130_fd_sc_hd.gds) and replaces every cell abstract with a reference to the full cell layout.

The result is checked by DRC and LVS, which work on the real polygons. In the counter, the DEF is 48 kB of text; the GDSII additionally contains the full layouts of the 14 different cell types the design uses, fillers and taps included.

Running It in ChipVerify Lab

Run Place and Route on the counter. The report has a link to download the GDSII. Open it in KLayout on your own computer, load the sky130 layer properties, and descend into one of the cells to see its transistors.

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