Layout versus schematic (LVS) checks that the layout is the circuit the netlist describes: the same devices, connected the same way. It extracts transistors and their connections from the polygons of the GDSII and compares them with the netlist. DRC can pass on a layout with VDD shorted to VSS; LVS cannot. This article runs LVS on the routed 16x16 multiplier with Magic and Netgen, works through the setup problems that make a first LVS run fail on a correct layout, and then shows how a real open and a real short are reported.
8 min read | Intermediate
What You'll Learn
- Describe the extraction and comparison steps of LVS
- Tell setup mismatches from real layout errors
- Read Netgen's report for an open and a short
- Explain why the netlist side needs body pins and matching names
The Two Sides of LVS
- Layout side. Magic reads the GDSII, recognizes devices from layer combinations (poly over diffusion is a transistor, the implant decides n or p), traces every conducting layer through contacts and vias, and writes the circuit it found as a SPICE netlist.
- Schematic side. The design's netlist, written from the placed and routed database, plus the transistor-level netlist of every standard cell from the library.
- Comparison. Netgen matches the two circuits as graphs: devices are nodes, nets are edges. If every device and net in one has a unique partner in the other, the circuits match.
The steps, as run on the multiplier:
# 1. netlist of the routed design (OpenROAD) write_cdl -masters sky130hd.cdl layout.cdl # 2. extract the layout (Magic) gds read layout.gds load mult16 extract all ext2spice lvs ext2spice -o lvs_extracted.spice # 3. compare (Netgen) netgen -batch lvs "lvs_extracted.spice mult16" "lvs_schematic.spice mult16" sky130A_setup.tcl lvs_report.txt
The setup file sky130A_setup.tcl from the PDK tells Netgen which devices are equivalent, which properties to compare and which cells to treat as black boxes. Magic took 361 seconds to extract the multiplier; Netgen compared it in under a second.
First Runs Fail on Setup
The layout of the multiplier is correct: it was routed by the tool and passes DRC. Yet the first LVS runs failed three times, each for a reason in the setup, not in the layout. These are the usual first problems in any new LVS flow.
1. Floating body pins
Circuit 1 contains 11128 devices, Circuit 2 contains 11128 devices. Circuit 1 contains 50130 nets, Circuit 2 contains 52728 nets. *** MISMATCH ***
Every transistor was there, but the netlist side had 2,598 nets too many, almost exactly two per standard cell. Each sky130 cell has two body pins, VPB (n-well) and VNB (p-substrate), besides VPWR and VGND. The netlist was written from a database whose cell abstracts had no body pins, so every cell instance got two unconnected nets: X_1203_ ra\[4\] rb\[10\] VSS _unconnected_0 _unconnected_1. In the layout, the bodies are tied to VDD and VSS through the tap cells. Writing the netlist from cell abstracts that do define VPB and VNB, with them connected to VDD and VSS, made the net counts equal.
2. Escaped names
The netlist writer escaped the brackets of bus names, a\[13\], while Magic wrote a[13]. Netgen then found no port with the same name on both sides and could not anchor the comparison at the pins. Removing the escapes fixed the port list.
3. Different device names
The library's CDL netlist calls the transistors nfet_01v8 and pfet_01v8_hvt with pins named proxy1 to proxy4, while Magic extracts them as sky130_fd_pr__nfet_01v8 with pins named after drain, gate, source and bulk. The setup file treats both as black boxes, and boxes with different pin names never match. Using the library's SPICE netlist, which uses the same device names as the extraction, removed the last mismatch:
Circuit 1 contains 1283 devices, Circuit 2 contains 1283 devices. Circuit 1 contains 1318 nets, Circuit 2 contains 1318 nets. Final result: Circuits match uniquely.
With both sides using the same cell definitions, Netgen first matched every cell type on its own, then compared the top level with each cell as a single device: 1,283 cell instances and 1,318 nets.
Quick Check
Q: The first run had identical transistor counts but 2,598 extra nets on the netlist side. Why is that a sign of a setup problem rather than a layout error?
Show Answer
A layout error such as an open or a short changes a few nets, not thousands, and the difference would not be an exact multiple of the cell count. Two extra nets per cell points to something every cell has in common: here, the two body pins left unconnected in the netlist.
A Real Open
To see a real error, the routing of one net, _0003_, was deleted from the DEF before the GDSII was written. The net connects a NAND output to an XNOR input with a short met1 wire. The netlist still has the net; the layout no longer has the wire. Netgen:
Net: sky130_fd_sc_hd__nand2_1_88/Y |Net: _0003_
sky130_fd_sc_hd__nand2_1/Y = 1 | sky130_fd_sc_hd__nand2_1/Y = 1
| sky130_fd_sc_hd__xnor2_1/B = 1
Net: sky130_fd_sc_hd__xnor2_1_74/B |(no matching net)
sky130_fd_sc_hd__xnor2_1/B = 1 |
Final result: Netlists do not match.
The left column is the layout, the right the netlist. In the netlist, net _0003_ connects a NAND output and an XNOR input. In the layout these are two separate nets with one pin each, named by Magic after the pin they touch. That is the signature of an open: one schematic net split into several layout nets.
A Real Short
Next, a met1 strap was drawn from a VSS rail to the neighbouring VDD rail. The layout passed DRC, as shown in Design Rule Checking. LVS:
Circuit 1 contains 1283 devices, Circuit 2 contains 1283 devices. Circuit 1 contains 1317 nets, Circuit 2 contains 1318 nets. *** MISMATCH *** Net: VSUBS |(no matching net) sky130_fd_sc_hd__o22a_1/VGND = 11 | sky130_fd_sc_hd__o22a_1/VPWR = 11 | sky130_fd_sc_hd__o22a_1/VNB = 11 | sky130_fd_sc_hd__o22a_1/VPB = 11 | ...
The layout has one net fewer, and that net connects the VGND and VPWR pins of every cell: power and ground have merged. That is the signature of a short: two schematic nets merged into one layout net. Here the short is between the two supplies, so every cell in the design appears in the report, which makes it easy to recognize and hard to locate. Tools that highlight the merged net in the layout, or a search for the shortest path between the two supplies, find the strap.
Quick Check
Q: An LVS report shows the layout with one net more than the schematic. Is that more likely an open or a short?
Show Answer
An open. Breaking a wire splits one net into two, so the layout gains a net. A short joins two nets into one, so the layout loses a net, as with the VDD-VSS strap, which left the layout at 1,317 nets against 1,318.
Running It in ChipVerify Lab
The lab's flow runs LVS on every Place and Route job, with the fixes described above: write_cdl writes the routed netlist with the cells' body pins, the bus names are unescaped, Magic extracts the GDSII, and Netgen compares the two against the published sky130 SPICE cell netlists. Run the multiplier and open the LVS section of the report: it shows a match with 1,286 devices and 1,318 nets on both sides, and the full Netgen report can be opened from it. If a run reports a mismatch, read the device and net counts first, as in the exercise below.
Common Mistakes
Mistake #1: Debugging the layout before the setup
Large, regular mismatches, such as two extra nets per cell or no matching ports at all, come from the netlists and the setup. Fix those before looking for opens and shorts.
Mistake #2: Forgetting body and well connections
Cells with separate body pins need them in the netlist, connected the way the taps connect them in the layout.
Mistake #3: Signing off without LVS
DRC passed a layout with VDD shorted to VSS. Only LVS checks that the polygons form the intended circuit.
Practice Exercise
Challenge: Reading Net Counts
Three LVS runs report, layout first: (a) 1,318 nets against 1,318, devices equal, but "Netlists do not match". (b) 1,320 nets against 1,318. (c) 1,316 nets against 1,318. What kind of error does each suggest?
Hint
An open adds layout nets, a short removes them. Equal counts can still hide errors.
Solution
(a) Equal counts but no match: nets are connected differently, for example two wires swapped, or a short and an open that cancel in the count. (b) Two extra layout nets: opens, such as one net split into three pieces or two nets each split in two. (c) Two missing layout nets: shorts merging nets together. In every case the net and device listings in the report show which nets are involved.
Open the ready-made example in the lab, synthesize it and run Place and Route.
Summary
- LVS extracts devices and connectivity from the GDSII with Magic and compares them with the netlist in Netgen.
- A correct layout first failed on setup: floating body pins in the netlist, escaped bus names and different device names.
- With the setup fixed, the multiplier matched uniquely: 1,283 cells and 1,318 nets.
- An open splits a schematic net into several layout nets; a short merges nets, as the VDD-VSS strap did.
