Learn Chip Design & Verification

Free courses and a professional-grade lab to build and run your designs.

Browse courses Try the Lab !

Foundations

Chip Design Careers

Roles, companies, skills, interviews and how AI is changing chip work.

Digital Design

Gates, flip-flops, FSMs and the timing basics every chip engineer needs.

Verilog

Model and simulate digital hardware in the industry-standard HDL.

Computer Architecture

Instruction sets, pipelines, caches and how processors run code.

Bus Protocols

APB, AHB, AXI, UART, SPI and I2C, with simulations you can run.

Design & Implementation

SoC Design

Interconnects, memory, interrupts, clocks, power and tapeout.

RTL Synthesis

From Verilog to real gates with Yosys and SkyWater 130nm.

Static Timing Analysis

Setup, hold, clocks, constraints and timing reports.

Physical Design

Floorplan, place, build the clock tree and route to layout.

Power Format (UPF)

Power domains, isolation, retention and switching.

Verification

Verification

Constrained-random tests, coverage and verification planning.

SystemVerilog

Classes, constraints, assertions and coverage.

UVM

Reusable, scalable testbenches with the UVM methodology.

Formal Verification

Prove properties with model checking, induction and equivalence.

SoC Verification

Whole-chip tests: C on the CPU, interconnects, interrupts and DMA.

Post-Silicon Validation

Bring-up, debug and characterization on real silicon.

Browser-Based EDA Platform

From RTL to Layout — No Installation Needed

ChipVerify™ Lab gives you professional-grade chip design tools in your browser. Write Verilog, SystemVerilog and UVM, run simulations, synthesize with the SkyWater 130nm PDK, analyze timing, and take your design through place & route, DRC and LVS — all from one platform.

Icarus Verilog & Verilator simulators
SystemVerilog & UVM testbenches
Yosys synthesis with SkyWater PDK
Static timing analysis (OpenSTA)
Place & route with OpenROAD
DRC & LVS checks, GDSII layout
Formal verification (SymbiYosys)
Waveforms, schematics & coverage
Lint checking & FSM extraction
GitHub sync & shareable links

Try the Lab ! Read the Guide

ChipVerify Lab - Verilog Simulation

Verilog Simulation with Waveform Viewer

ChipVerify Lab - RTL Synthesis

RTL Synthesis with SkyWater PDK

Recommended Learning Path

Start with the foundations, then follow the track for the role you want.

Start here

0 Chip Design Careers Optional How the chip industry works, the roles in it, and which track fits you. 1 Digital Design Logic gates, flip-flops, FSMs and timing: the foundation everything else builds on. 2 Verilog Describe hardware in the industry-standard HDL and simulate what you build. 3 Computer Architecture How a processor runs programs: instructions, pipelines, caches and memory. 4 Bus Protocols How blocks talk: handshakes, APB, AHB and AXI, plus UART, SPI and I2C.

Design track

For RTL, synthesis and physical design roles

5 SystemVerilog for Design The synthesizable subset: logic, enums, structs, always_ff, interfaces and packages. 6 SoC Design Plan a whole chip: buses, memory, interrupts, clocks, power and sign-off. 7 RTL Synthesis Turn Verilog into real gates with Yosys and the SkyWater 130nm PDK. 8 Static Timing Analysis Check that every path meets timing: setup, hold, clocks and constraints. 9 Physical Design Floorplan, place, build the clock tree and route: from netlist to layout. + Power Format (UPF) Optional Add power domains, isolation and retention for low-power chips.

Verification track

For design verification (DV) roles

5 Verification Testbenches, constrained-random stimulus, checking and functional coverage. 6 SystemVerilog Classes, interfaces, randomization and assertions for modern testbenches. 7 UVM Build reusable, scalable testbenches the way chip companies do. 8 Formal Verification Prove properties for every input instead of simulating a few. 9 SoC Verification Verify whole chips: C tests on the CPU, interconnects, interrupts and DMA. 10 Post-Silicon Validation Bring up and debug the real chip, from first power-on to production.