Besides DRC and LVS, sign-off includes three groups of checks that look at the layout from other angles: antenna rules, which protect gates during manufacturing; electrical rule checks (ERC), which look for floating nets, broken supplies, electrical limits and missing constraints; and density rules, which keep each metal layer even enough to polish. This article runs each on the routed 16x16 multiplier and reads the results, including two findings that only a full check list catches.
7 min read | Intermediate
What You'll Learn
- Place the antenna check in the sign-off flow
- Run electrical rule checks in OpenROAD and read their results
- Find unconstrained paths with a constraint check
- Explain why density is a chip-level check and what its sky130 limits are
Antenna Check
The antenna effect and its fixes are described in The Antenna Effect and Diode Insertion. For sign-off, what matters is that the final check runs on the final routes, after every repair and ECO:
check_antennas -report_file antenna.rpt
The lab's flow runs it after detailed routing, once its antenna repairs are done: one after global routing and up to three after detailed routing, stopping as soon as a pass no longer reduces the count. Across the runs in this tutorial, the multiplier at 44 % utilization was clean, denser placements of the same design had up to 6 violating nets without repair, and the clock-gated register file had 12 without repair and none after the lab's repairs. Around a macro some nets resist repair: the SRAM wrapper at 30 % ended with 3 after three passes. Each violation is a gate that can be damaged during manufacturing, so the count must be zero at tapeout, by diodes, jumpers or rerouting, followed by a new check.
Electrical Rule Checks
ERC covers electrical problems that are neither geometry nor timing. OpenROAD and its timer provide several of them. They were run on the routed and extracted multiplier:
report_floating_nets -verbose check_power_grid -net VDD -dont_require_terminals check_power_grid -net VSS -dont_require_terminals report_check_types -max_slew -max_capacitance -max_fanout check_setup -verbose
Floating nets and power grid
report_floating_nets reported no floating nets. The power grid check confirmed that every shape of each supply is connected:
[INFO PSM-0040] All shapes on net VDD are connected. [INFO PSM-0040] All shapes on net VSS are connected.
Without the -dont_require_terminals option, the same check stopped with PSM-0025 VDD does not contain any terminals. The block has no power pins: its grid is complete inside, but nothing marks where the supplies enter. For a block that will be placed inside a larger chip, the top-level straps must be exported as pins so the chip-level grid can connect to them. A connectivity check of a single block has to assume where the supply comes from.
Electrical limits
max slew Pin Limit Slew Slack _2416_/Q 1.50 1.33 0.17 (MET) max capacitance Pin Limit Cap Slack _2416_/Q 0.16 0.14 0.02 (MET)
The Liberty file limits each cell's output slew and load capacitance, and the extracted layout must respect them: outside the limits, the cell's timing tables are not valid and the timer's numbers mean little. The worst pin, an operand register driving a large part of the multiplier array, is within both limits, but with only 0.02 pF of capacitance margin. The fanout limit reports nothing in sky130, because the library gives every pin a fanout load of zero, as explained in Design Repair.
Missing constraints
The most important finding came from check_setup:
Warning: There are 32 input ports missing set_input_delay. Warning: There are 64 unconstrained endpoints.
The flow defines the clock and nothing else. Without input and output delays, no path from an input port to the first register, or from the last register to an output port, has a timing requirement. The first warning lists the 32 inputs a and b; the 64 unconstrained endpoints are the 32 product outputs p and the D pins of the 32 operand registers, which are fed directly from the inputs. Every slack reported for this design covered only the register-to-register paths. A design with no setup violations can still fail in the chip if its I/O paths were never timed.
Quick Check
Q: The timing report of the multiplier showed no violations at 10 ns. Why does the 64 unconstrained endpoints warning still matter?
Show Answer
An unconstrained endpoint has no required time, so it can never appear as a violation, however late its data arrives. The clean report only proves that the constrained paths meet timing. The paths through the inputs and outputs were never checked, and in the real chip they have to meet the timing of whatever drives and receives those signals.
Density Checks
Each metal layer must have an even amount of metal for chemical-mechanical polishing, as described in Fillers, Metal Fill and Density Rules. The sky130 PDK checks density with a Magic script, check_density.py, which measures each layer in windows of 700 x 700 um, stepped by 70 um across the chip. Its limits:
| Layer | Minimum density | Maximum density |
|---|---|---|
| Diffusion (FOM) | 33 % | 57 % |
| li1, met1, met2, met3, met4 | 35 % | 60 % |
| met5 | 45 % | 76 % |
Run on the multiplier, the script stopped immediately:
Layout is < 700um x 700um; cannot run density checks.
The block is 175 um square, a sixteenth of one window. Density is a property of the whole chip, checked after all blocks, the I/O ring and the chip-level fill are in place. The KLayout DRC deck used in Design Rule Checking has no density rules for the same reason.
The block still matters at chip level. After metal fill, its layers were at 19.8 % (met1), 9.5 % (met2), 21.0 % (met3), 32.5 % (met4) and 16.0 % (met5), all below the minimums. A window that contains this block needs denser metal or fill in the rest of the window to reach 35 %, and blocks that leave large empty regions make that harder. The filled layout itself passed DRC with no violations: the fill shapes followed the spacing rules.
Quick Check
Q: met2 was at 9.5 % in the filled block. Can the chip still meet the 35 % minimum in a window that contains the block?
Show Answer
Possibly. The window is 16 times larger than the block, so the rest of the window, other blocks, routing and chip-level fill, can bring the average up. A block at 9.5 % covering a sixteenth of the window lowers the average by about 1.6 points compared with a block at 35 %. If many blocks are sparse, chip-level fill has to make up the difference.
Running It in ChipVerify Lab
Run Place and Route on the multiplier and open the Antenna section of the report, and the post-route STA report for slew and capacitance. The lab's flow sets input and output delays of 20 % of the clock period on every port (PRO users can change the percentage), runs check_setup and report_floating_nets at the end, and writes both to the checks section of the report. For the multiplier it reads check_setup: no missing I/O delays, unconstrained endpoints, unclocked registers or loops and report_floating_nets: no floating nets. A metal density section reports the density of each layer of the block, as information, since the 700 um windows of the rule are larger than the block.
Common Mistakes
Mistake #1: Ignoring constraint warnings
Unconstrained endpoints never fail timing. Run check_setup and treat missing input and output delays as an error at sign-off.
Mistake #2: Reading block-level density as chip-level density
Density windows are larger than most blocks. A block-level number is an input to the chip-level fill, not a pass or fail.
Mistake #3: Running antenna checks before the last routing change
Every ECO and reroute can create new antenna ratios. The check that counts is the one on the final routes.
Practice Exercise
Challenge: Constraining the I/O Paths
The multiplier's inputs come from registers in a neighbouring block whose outputs arrive 2 ns after the clock edge, and its outputs must be stable 3 ns before the next edge at the receiving block. Write the constraints for a 10 ns clock on port clk. How much of the clock period is left for the paths from the inputs to the operand registers?
Hint
Input delay is the time already used outside the block; output delay is the time needed outside the block.
Solution
set_input_delay 2.0 -clock clk [get_ports {a* b*}] and set_output_delay 3.0 -clock clk [get_ports {p*}]. An input path then has 10 - 2 = 8 ns, minus the setup time of the operand register, to get from the port to the register. With these two lines on the routed multiplier, check_setup printed no warnings, and the I/O paths appeared in the timing report: the worst input path met timing with 8.23 ns of slack and the worst output path with 6.29 ns. (In this OpenSTA version, a bus pattern written as a[*] is rejected; a* matches the same ports.)
Open the ready-made example in the lab, synthesize it and run Place and Route.
Summary
- The antenna check must be zero on the final routes; the tutorial's runs had 0 to 12 violating nets depending on design and density.
- ERC on the multiplier found no floating nets, a fully connected grid without power pins, and slew and capacitance within limits.
check_setupfound 64 unconstrained endpoints: none of the I/O paths had ever been timed.- sky130 density is checked in 700 um windows with 35 to 60 % limits for most metals, so it is a chip-level check; the block's filled layers were all below 35 %.
