Timing ECOs

Late in a project, a design is almost finished. The layout is done, the clock tree is built, the checks nearly pass, and a few paths still fail. Running the whole flow again would change everything and take days. An engineering change order, an ECO, fixes the remaining violations by editing a small number of cells and wires and leaving the rest untouched. This article explains what a timing ECO is, how it is done, what it costs, and what must be checked afterwards.

8 min read | Intermediate

What You'll Learn

• Define a timing ECO and say when it is used instead of a new run of the flow
• Describe the steps of an ECO loop
• Choose a fix for a setup or a hold violation and estimate its effect
• List the checks that a design needs after an ECO

What an ECO Is

An ECO is a small, targeted change to a design that is already implemented. A timing ECO is one whose purpose is to fix timing violations, and it does not change the function of the design. The typical changes are:

• Swapping a cell for a larger or smaller one, or for another threshold version.
• Inserting a buffer or a delay cell.
• Changing a cell for a different arrangement of gates that has the same function.
• Moving a cell, or changing a short piece of the routing.

The word is also used for functional ECOs, which fix a bug in the logic. The mechanics are the same, but a functional change must be verified in a different way.

Why Not Run the Flow Again

Every run of the implementation tools changes the placement, the clock tree and the routing of the whole design. The violations that were fixed come back in other places, and the process may not converge. Near the end, the team wants the opposite: keep the 99 percent that works and change only what has to change. An ECO keeps the placement and the routes of all other cells in place, so that the timing of the rest of the design stays as it was.

The Loop

1. Run STA at all the corners and modes, and collect the violations, setup and hold.
2. For each violation, choose a fix from the techniques of the optimization article. The tools can suggest changes, and a designer can adjust them.
3. Edit the netlist. Only a few cells change.
4. Place the new cells in free space near the old ones and route the changed nets, without moving anything else.
5. Extract the changed parasitics and run STA again.

The loop is repeated until no violation remains. A fix for one corner can break another, so the run covers all of them each time.

Two Examples

These come from the earlier articles. First, a hold violation. A path from one flip-flop to the next with a late capture clock had a hold slack of -0.0904 ns. One delay cell dlygate4sd3_1 in the data path adds 0.5205 ns, and the hold slack becomes +0.4330 ns. The same cell takes the setup slack of that path from 2.0200 ns to 1.4801 ns. The ECO has one new cell, and the path has enough setup slack to pay for it.

Second, a setup violation. A path with a 4-input OR cell had a slack of -0.0585 ns. Replacing that one cell by two NOR gates and a NAND gate gave +0.2339 ns, and it costs 3.75 um2 of area. The ECO removes one cell and adds three, and the three have to find space near the old position.

Estimating the effect before the change saves loops. The delay of the new cell is known from the library, and the old delay is in the report, so the new slack is the old slack plus the change of the delays on the path. The tool then confirms the number with a real run, which also includes the new wire.

Spare Cells and Metal-Only ECOs

When a chip has already been sent to manufacturing, the cost of a change is much higher, because each change of a manufacturing layer needs a new mask. Teams scatter spare cells, unused gates of several types, over the chip. A late ECO then reuses a spare cell and changes only a few metal layers, which are the last masks. This is called a metal-only ECO. The design rule is the same: change as little as possible.

What to Check After an ECO

• Timing at all corners and modes, setup and hold, including crosstalk. The new cell changes the capacitance and the neighbours of some wires.
• Design rules: maximum transition, capacitance and fanout of the changed nets.
• Function: an equivalence check between the netlist before and after the ECO, to make sure that the change did not alter the logic.
• Physical rules: the new cell fits, the routes pass the layout checks, and the power grid is intact.
• The paths that were not touched. A new cell can change the timing of a neighbour through shared nets or crosstalk.

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