Input and Output Delays

Inside the chip, STA knows every clock edge and every delay. At the ports it knows nothing, because the outside world is not part of the design. Input delay and output delay are the two commands that describe it. They say how much of the clock period the outside logic uses. This article explains what they mean, why each has a minimum and a maximum value, and how they change the setup and hold slack of the port paths.

9 min read | Intermediate

What You'll Learn

• Explain what an input delay and an output delay describe
• Use the -max and -min options and say which check each one belongs to
• Calculate the arrival and required times of an input path and an output path
• Use -rise, -fall and -add_delay when the data needs more than one value

Input Delay

An input delay says how late the data at an input port arrives, measured from the clock edge that launches it in the outside device. The outside device has its own clock-to-Q delay and its own wires, and the input delay holds all of that:

set_input_delay 0.4 -clock clk [get_ports {a b c d}]

The data at the ports a to d arrives 0.4 ns after the edge of clk. For the path from the input c to a flip-flop, the arrival time is the input delay plus the delay of the logic, so the logic has the rest of the period. With a period of 2.0 ns, 0.4 ns is used outside the chip.

Output Delay

An output delay says how much time the outside device needs after the data leaves the chip. It includes the wires outside the chip and the setup time of the flip-flop that captures the data there:

set_output_delay 0.4 -clock clk [get_ports {y z}]

The data at y and z must be there 0.4 ns before the next clock edge. The required time at an output port is the clock period minus the output delay, 2.0 - 0.4 = 1.6 ns.

Minimum and Maximum

The outside device does not always take the same time. Its delay depends on the data, on the temperature and on the transition. For setup you need the largest delay, for hold the smallest. The options -max and -min give the two values:

set_input_delay  -max 0.6 -clock clk [get_ports {a b c d}]
set_input_delay  -min 0.2 -clock clk [get_ports {a b c d}]
set_output_delay -max 0.5 -clock clk [get_ports {y z}]
set_output_delay -min -0.1 -clock clk [get_ports {y z}]

When you give a single value without -min or -max, STA uses it for both. That is what the demo constraints do. The diagram shows the effect of an input delay with a window between 0.2 ns and 0.6 ns. The data at the port may change anywhere inside the window, so STA uses the late end for setup and the early end for hold:

The path report shows the two input delays with the transition symbol. The setup report has a row 0.6000 v input external delay and the hold report has 0.2000 ^ input external delay.

Output Delay Min and Max

For an output, the roles are the opposite way round. The maximum output delay is the setup requirement of the outside device, and it reduces the required time for setup. The minimum output delay is the hold requirement of the outside device. A hold requirement can be negative, as in the example with -min -0.1, which means that the outside device accepts the data to change slightly before the clock edge.

For the path from a flip-flop through an AND gate to the output y:

Rise, Fall and More Than One Clock

Some devices are slower for a rising output than for a falling one. The options -rise and -fall set a different value for each transition, as shown in the article about timing arcs.

A port can also be launched or captured by more than one clock, for example when the outside device runs in two modes. A second set_input_delay for the same port with a different clock replaces the first one unless you add the option -add_delay. With -add_delay both constraints stay, and STA checks the paths for both clocks. Another option, -clock_fall, tells STA that the delay is measured from the falling edge of the clock, which is used for devices that launch or capture on that edge.

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