Timing in Placement and Clock Tree Synthesis

After synthesis, the design goes to physical implementation. Placement puts every cell at a place on the chip, and clock tree synthesis builds the network that delivers the clock to every flip-flop. Both steps change timing: placement fixes the distances, and the clock tree creates skew and a real clock latency. This article explains what happens to timing in each of the two steps, shows the effect of the clock tree with real numbers, and says why hold fixing comes after it.

8 min read | Intermediate

What You'll Learn

• Describe what the placement tool does with timing information
• Explain what clock tree synthesis builds and what it tries to achieve
• Read the change of setup and hold slack when the clock changes from ideal to propagated
• Say why hold violations are fixed after the clock tree is built

Timing in Placement

Placement decides where each cell sits. The tool has a timing engine and uses it to place the cells of critical paths close together, so that their wires are short. It estimates the wire delay from the positions, for example with a simple model of the length of the wire, and updates the slack as cells move. Typical actions during placement are:

• Moving the cells of a critical path next to each other, and away from the cells of paths that have plenty of slack.
• Sizing cells and adding buffers, as the synthesis tool did, now with a better idea of the wires.
• Splitting nets with a large fanout.
• Avoiding congestion, because a crowded area forces long detours of the wires.

At this stage the clocks are still ideal. The tool assumes that all flip-flops get their clock at the same moment, and it optimizes the data paths. The wire estimates are better than a wire load model, but they are not the final routes.

Clock Tree Synthesis

A clock net can have thousands of flip-flop pins. One driver cannot drive them all with a sharp edge, and the wires have different lengths. Clock tree synthesis builds a tree of buffers from the clock port to the flip-flops. The goals are:

• A small skew between flip-flops that exchange data. The tool balances the delay of the branches.
• A good edge, with a slew that is within the limits, at every clock pin.
• A small area and power. Clock buffers use a large part of the dynamic power of a chip.
• Robustness against variation, which means that the branches share as much of the path as possible.

The tree gets its delay by itself. The clock now arrives later at the flip-flops, by the latency of the tree, and different flip-flops get it at slightly different times.

What Changes in the Report

Before the tree, the clock is ideal. After it, the clock is propagated, which means STA follows the buffers of the tree, as in the article about clock latency. The tree of that article has a root buffer and two branches, with the clock arriving at 0.1701 ns at the first flip-flop and at 0.2435 ns at the second:

The skew of 0.0734 ns, with the capture clock later, gives setup 0.07 ns more and hold 0.07 ns less. This is the usual pattern: a clock tree changes hold more than setup, because skew moves both in opposite directions and hold has a smaller margin to begin with. In a real design, a skew of 0.1 ns can be enough to make hold fail for a pair of flip-flops with a short path between them.

Why Hold Fixing Comes After the Tree

Before the tree exists, the clock skew is unknown. The hold slack that the tool sees with ideal clocks is not the one that the chip will have. If the tool tried to fix hold at that point, it would add delay cells where no real violation exists, and it would miss the places where the tree creates one. The usual order is:

1. Place the cells and optimize setup with ideal clocks.
2. Build the clock tree.
3. Switch to propagated clocks, check setup again, and fix hold with delay cells and sizing, as in the article about fixing hold violations.
4. Route the wires, extract the parasitics, and repeat the checks and the fixes with the real wires and with crosstalk.

The fixing of hold costs area and some setup slack, as shown in that article. Teams try to keep the skew small so that the number of fixes stays low.

Useful Skew in the Flow

Some clock tree tools can build the tree with an intended skew, using the delay of the capture clock to help a failing path. This is the useful skew of the article about clock skew, and the tool checks that the hold slack and the neighbouring paths stay positive.

Common Mistakes

set_clock_latency 0.0734 [get_pins _6_/CLK]