Common Path Pessimism Removal

The reports in the earlier articles had a row called clock reconvergence pessimism, and its value was always zero. With on-chip variation derates it is no longer zero, and it is one of the most useful rows in a timing report. Common path pessimism removal, CPPR, also called CRPR, takes back a margin that the derates added by mistake. This article explains where that pessimism comes from, how the credit is calculated, and shows the effect on setup and hold slack with real numbers.

8 min read | Intermediate

What You'll Learn

• Explain what the common part of two clock paths is and why derating it is wrong
• Calculate the CPPR credit from the late and the early delay of the common part
• Read the CPPR row in a setup report and in a hold report
• Compare the slack with and without CPPR

The Common Part of the Clock Path

The launch flip-flop and the capture flip-flop get their clock from the same source. In a real clock tree, the clock first goes through some shared buffers, and then it splits and goes to the two flip-flops through separate branches. The shared part is the common path. In the clock tree used in the earlier examples, the root buffer is common to both flip-flops:

Now think about the derates. For setup, the launch clock path is late and the capture clock path is early. If STA applies this to the whole of both paths, it counts the root buffer as slow for the launch and as fast for the capture. But it is the same physical buffer, and one buffer on one chip has one delay. It cannot be slow for one flip-flop and fast for the other at the same moment. This is pessimism, and it has nothing to do with the real variation between different cells.

The Credit

CPPR finds the last point that both clock paths share, and it gives back the difference of the two delays of the common part. In our example, the root buffer has a late delay of 0.1113 ns and an early delay of 0.0911 ns:

CPPR credit = late arrival at the common point - early arrival at the common point
            = 0.1113 - 0.0911 = 0.0202 ns

The branches that are not shared, one buffer for the launch flip-flop and two for the capture flip-flop, keep their derates. These differences are real, because different cells vary differently. Only the common part is corrected.

In the Reports

The credit appears in the row clock reconvergence pessimism of the capture clock path. For the setup check of the example, it is added to the required time:

   2.0000    2.0000   clock clk (rise edge)
   0.0911    2.0911 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
   0.0643    2.1554 ^ b2a/X (sky130_fd_sc_hd__clkbuf_1)
   0.0638    2.2191 ^ b2b/X (sky130_fd_sc_hd__clkbuf_1)
   0.0000    2.2191 ^ r2/CLK (sky130_fd_sc_hd__dfxtp_1)
   0.0202    2.2393   clock reconvergence pessimism
  -0.1029    2.1364   library setup time
             2.1364   data required time
             1.6396   slack (MET)

The credit of +0.0202 ns moves the capture clock later, which gives the data more time. Without CPPR, the required time would be 2.1162 ns and the setup slack 1.6194 ns. For hold, the credit has the opposite sign, because the capture clock path is late and the launch clock path is early. It is subtracted from the required time:

   0.2678 ^ r2/CLK (sky130_fd_sc_hd__dfxtp_1)
  -0.0202    0.2476   clock reconvergence pessimism
  -0.0300    0.2176   library hold time
             0.2176   data required time
             0.1945   slack (MET)

Both slacks improve by the same amount. In OpenSTA, CPPR is on by default. The variable sta_crpr_enabled can be set to 0 to switch it off, which is how the numbers without CPPR were produced.

When the Credit Is Zero

With no derates, the late and the early delay are equal, and the credit is zero. This is the case for all the examples before the chapter about variation. The same happens for a path whose launch and capture flip-flops are the same cell, or for an input port path, where there is no common clock path. And with ideal clocks, there are no clock cells at all.

Why It Matters

The credit is small in this example, 0.0202 ns, because the common path is a single buffer. In a real chip, the clock tree has many levels, and two flip-flops of the same block often share most of them. The common part can be hundreds of picoseconds long, and the credit is a percentage of it, for example 20 percent for a late derate of 1.1 and an early derate of 0.9. Without CPPR, many paths between flip-flops that are close together would fail for the wrong reason. The paths where it matters most are those between flip-flops that are physically close: they share a lot of the clock tree and have very little real clock variation between them.

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