Multicycle Paths

STA assumes that data launched at one clock edge is captured at the next one. Sometimes a design is built so that the data takes two or more cycles. The receiving flip-flop may only load a new value every other cycle, for example. Then the one-cycle rule is too strict and reports violations that are not real. A multicycle path tells STA how many cycles the data may take. This article explains the setup and the hold multipliers, and shows the common trap: a multicycle setup that breaks hold.

9 min read | Intermediate

What You'll Learn

• Explain when a path really takes more than one clock cycle
• Write set_multicycle_path for setup and for hold
• Say how the setup multiplier moves the hold check
• Calculate the setup and hold slack of a multicycle path

The Default: One Cycle

For the path from _7_ to _6_ in the demo circuit, the launch edge is at 0 and the capture edge for setup is at 2.0 ns, one clock period later. The hold check uses the capture edge at 0, the same edge as the launch. The setup slack is 1.4502 ns and the hold slack is 0.4241 ns.

Suppose the second flip-flop only uses its data every second cycle. A design with a slow enable signal does this: the first flip-flop changes its value, the logic needs a long time to settle, and the second flip-flop is enabled two cycles later. The data has two periods to arrive, but STA still checks it against the first edge, and reports a violation on a path that works. A multicycle path moves the capture edge.

The Setup Multiplier

The command set_multicycle_path takes the number of cycles and the check it applies to:

set_multicycle_path 2 -setup -from [get_pins _7_/CLK] -to [get_pins _6_/D]

The setup capture edge moves from the edge at 2.0 ns to the edge at 4.0 ns. The required time grows by one period, and the setup slack becomes 3.4502 ns:

   2.0000 ... clock clk (rise edge)
             4.0000 ^ _6_/CLK (sky130_fd_sc_hd__dfxtp_1)
  -0.1174    3.8826   library setup time
             3.8826   data required time
            -0.4323   data arrival time
             3.4502   slack (MET)

The Hold Trap

The hold check is defined relative to the setup check. By default it uses the edge one cycle before the setup capture edge. When the setup edge moves to 4.0 ns, the hold edge moves to 2.0 ns. The hold check then asks that the data does not arrive before 2.0 ns, and it arrives at 0.3657 ns:

   0.0000    2.0000   clock clk (rise edge)
             2.0000 ^ _6_/CLK (sky130_fd_sc_hd__dfxtp_1)
  -0.0583    1.9417   library setup time
             1.9417   data required time
            -0.3657   data arrival time
            -1.5759   slack (VIOLATED)

A multicycle setup command alone gives a hold violation of -1.5759 ns, which is about one clock period. The data was never supposed to be that slow. STA now believes that the data launched at 0 must not arrive before the capture edge at 2.0 ns, which would mean that the data has to be slower than one clock cycle. That is not what you meant. In a real multicycle design, the second flip-flop ignores the edge at 2.0 ns, because its enable is off, so the only hold check that matters is the one at the launch edge, where it was before. The second command, with the hold multiplier, puts it back:

set_multicycle_path 2 -setup -from [get_pins _7_/CLK] -to [get_pins _6_/D]
set_multicycle_path 1 -hold  -from [get_pins _7_/CLK] -to [get_pins _6_/D]

The hold multiplier of 1 moves the hold edge back by one cycle from where the setup multiplier put it. Together, the two commands give a setup slack of 3.4502 ns and a hold slack of 0.4241 ns, which is the original hold slack. The rule to remember is that a multicycle setup of N goes with a multicycle hold of N-1.

The Design Must Match the Constraint

A multicycle path is a promise. The constraint only says what STA should check. The circuit must really behave that way, for example with an enable that is true only every second cycle. If the data actually changes at every clock edge, the capture flip-flop will see the wrong value, and STA will not warn you. The usual way to be sure is to check the enable logic in simulation or formal checks, because STA cannot do it.

Different Clock Frequencies

A multicycle path can also be used with two clocks of different periods. The multiplier is counted in cycles of the capture clock for setup, and in cycles of the launch clock for hold, unless you choose otherwise with -start and -end. These options decide which clock the cycles are counted in. For one clock, which is the case in this article, they have no effect.

Common Mistakes

set_multicycle_path 3 -setup -from [get_pins _7_/CLK] -to [get_pins _6_/D]