Fixing Setup Violations

A setup violation means the data arrives too late. There are only a few ways to fix it, and each one has a price. This article shows a real violation, finds where the time is spent, and compares the common fixes using the numbers of the same path: pipelining, useful skew and a slower clock.

9 min read | Intermediate

What You'll Learn

• Find the slowest cells of a failing path in a timing report
• Name the main ways to fix a setup violation and what each one costs
• Calculate the minimum clock period that a path allows
• Check that a fix does not break hold or a neighbouring path

A Failing Path

This is the design from the article about clock skew. Two flip-flops with a small logic cone between them, and a 1.0 ns clock:

module sta_chain (input clk, input a, b, c, d, e, output q);
  reg r1, r2;
  always @(posedge clk) r1 <= a;
  wire w = (((r1 ^ b) & c) ^ (d | e)) & (r1 | d);
  always @(posedge clk) r2 <= w;
  assign q = r2;
endmodule

create_clock -name clk -period 1.0 [get_ports clk]
set_input_delay  0.2 -clock clk [get_ports {a b c d e}]
set_output_delay 0.2 -clock clk [get_ports q]

The worst setup path goes from the first flip-flop to the second one, and it fails:

      Cap      Slew     Delay      Time   Description
             0.0000    0.0000    0.0000 ^ _12_/CLK (sky130_fd_sc_hd__dfxtp_1)
   0.0055    0.0391    0.2863    0.2863 v _12_/Q (sky130_fd_sc_hd__dfxtp_1)
   0.0038    0.0481    0.1334    0.4197 v _06_/X (sky130_fd_sc_hd__and2_0)
   0.0023    0.0797    0.4542    0.8739 v _08_/X (sky130_fd_sc_hd__or4_1)
   0.0017    0.0849    0.1149    0.9888 ^ _10_/Y (sky130_fd_sc_hd__a21oi_1)
             0.0849    0.0000    0.9888 ^ _11_/D (sky130_fd_sc_hd__dfxtp_1)
                                 0.9888   data arrival time
                      -0.0697    0.9303   library setup time
                                -0.0585   slack (VIOLATED)

The diagram shows what the numbers mean. The data arrives at 0.9888 ns, but the latest allowed time is 0.9303 ns. The check is violated by 0.0585 ns. The first step in every fix is to look at the Delay column. Here the 4-input OR cell or4_1 takes 0.4542 ns, almost half of the whole path. A fix has to remove time from this path, or give the path more time.

The Minimum Period

Before changing anything, ask how slow the clock would have to be. The slack is 0.0585 ns short, so the period needs to grow by that much: 1.0 + 0.0585 = 1.0585 ns. In the tool, a period of 1.06 ns gives a worst setup slack of +0.0015 ns, and 1.2 ns gives +0.1415 ns. Often the clock speed is fixed by the product, so this fix is not available, but the number tells you how far you are from meeting timing.

Fix 1: Pipelining

If the logic is too long for one clock cycle, split it in two and put a register in the middle. Each half now has a full clock cycle:

module sta_pipe (input clk, input a, b, c, d, e, output q);
  reg r1, r2, m;
  always @(posedge clk) r1 <= a;
  wire s1 = ((r1 ^ b) & c);
  always @(posedge clk) m <= s1;
  wire w = (m ^ (d | e)) & (r1 | d);
  always @(posedge clk) r2 <= w;
  assign q = r2;
endmodule

With the same constraints, the worst setup slack becomes +0.2854 ns. The longest path now has two cells and is shorter than before. The price is that the result of the logic is available one clock cycle later, so the behavior of the design has changed, and the rest of the design must account for that. It also adds a flip-flop. This is the most powerful fix, and it is a design change, not just a tool setting. The chapter about timing closure covers it again.

Fix 2: Faster Cells and Simpler Logic

The synthesis and optimization tools can pick a stronger version of a cell, for example a larger transistor size that drives its load faster, or restructure the logic so that it has fewer levels. They try this automatically when the constraints are not met. The prices are area and power, and the larger cell loads the cell before it a little more. In the report, you look for the cell with the largest delay and for cells that drive a high load or have a slow input slew, such as the or4_1 in our path.

Fix 3: Useful Skew

If the next path has slack to spare, delay the clock of the capture flip-flop. With 0.1 ns of delay, the slack goes from -0.0585 to +0.0415 ns, as the article about skew showed. The price is that the next path loses 0.1 ns and the hold slack of this path loses 0.1 ns.

Fix 4: A Slower Clock

A longer clock period gives every setup check more time. Its price is the performance of the chip.

Check That the Fix Worked

After every change, run STA again and check three things:

• The failing path now has positive slack.
• The hold checks of the same path still pass. Skew and added logic both change them.
• The neighbouring paths still pass. A fix that moves time from one path to another can create a new violation.

Also be sure that the violation is real. A path that fails in STA but can never be used in operation can be removed from the checks with a timing exception, a topic of a later chapter. Never use an exception only to make a report clean.

Common Mistakes