Minimum Pulse Width and Minimum Period

A flip-flop is a small circuit with internal nodes that must be charged and discharged. If the clock pulse is too short, the internal nodes do not reach their values and the flip-flop can fail, whatever the data does. The minimum pulse width check protects against this. It looks at the clock waveform and the library, and no data is involved. This article explains the check, shows the numbers of a real flip-flop, and shows how the minimum period of a clock and of a whole design can be read from the reports.

7 min read | Intermediate

What You'll Learn

• Explain what the minimum pulse width check protects
• Read the high and low pulse limits of a library cell and the slack of the check
• Say how the clock waveform and the clock tree change the pulse width
• Find the minimum period of a design from the worst setup slack

The Check

The library gives two numbers for the clock pin of a flip-flop: the shortest high pulse and the shortest low pulse for which the cell is characterized. They are min_pulse_width tables in the Liberty file. STA compares the real pulses of the clock at that pin with them:

For the flip-flop dfxtp_1, the limits in our runs are 0.1551 ns for the high pulse and 0.1955 ns for the low pulse. For the clock of the demo circuit, with a period of 2.0 ns and a duty cycle of 50 percent, both pulses are 1.0 ns long, and the check has a lot of margin. The command report_check_types -min_pulse_width prints the pin with the smallest slack:

                                      Required    Actual
Pin                                      Width     Width     Slack
------------------------------------------------------------------
_6_/CLK (low)                           0.1955    1.0000    0.8045 (MET)

The pin _6_/CLK, low pulse, has the smallest slack of 0.8045 ns. The high pulse has a larger one, because its limit is smaller and the pulse is as long.

What Changes the Pulse Width

• The period and the duty cycle in create_clock. A clock of 2.0 ns with -waveform {0 0.5} has a high pulse of 0.5 ns, and the slack of the high pulse check is 0.5 - 0.1551 = 0.3449 ns.
• A faster clock. With a period of 0.5 ns and 50 percent duty, each pulse is 0.25 ns long, and the low pulse has a slack of 0.25 - 0.1955 = 0.0545 ns. At a period below about 0.39 ns the low pulse of this flip-flop would violate the check.
• The clock tree. A buffer or a gate can make the rising edge slower than the falling edge or the other way round, and a pulse gets shorter or longer on its way. With propagated clocks, STA includes this. The check matters most after the clock tree is built.

The check is applied at every clock pin of every cell that has a pulse width limit in the library: flip-flops, latches and memories. It also covers the pins of a clock gate. A clock that is generated by a divider has a pulse width that follows from the master clock.

The Minimum Period

There are two ways to speak of a minimum period. The first is a limit of a cell: some cells, such as memories, have a minimum clock period in the library, and the check compares the period of the clock with it. The library of the flip-flops in this tutorial has no such limit, and the command report_check_types -min_period prints nothing for the demo circuit.

The second is the minimum period of the design, which follows from the setup paths. The setup slack grows with the period in a simple way: each time you lengthen the period by some amount, the slack of every path that starts and ends at the same clock edges grows by the same amount. The smallest period at which the worst path just meets setup is:

Minimum period = current period - worst setup slack

In the demo circuit, the worst setup slack at 2.0 ns is 1.0326 ns, on the path from the input to the output. The minimum period is 2.0 - 1.0326 = 0.9674 ns, which is what the article about feedthrough paths found. In a design where the worst path is limited by something that does not change with the period, such as a max delay constraint, this simple rule does not apply.

Common Mistakes

create_clock -name clk -period 0.4 [get_ports clk]