Design Rule Constraints in SDC

The article about design rule checks explains what the maximum transition, capacitance and fanout limits protect. This article is about the SDC side: the commands that set the limits, where they can be applied, how they work together with the limits in the library, and which of them are useful in a real flow. The examples run on the demo circuit.

7 min read | Intermediate

What You'll Learn

• Set limits for the whole design, for ports and for nets with the SDC commands
• Read the limit, the actual value and the slack in a design rule report
• Explain how a limit on a port differs from a limit inside the design
• Know the limits of the fanout check with a library that has no fanout loads

The Three Commands

Each rule has one SDC command:

set_max_transition  0.5 [current_design]
set_max_capacitance 0.03 [get_ports a]
set_max_fanout      8 [current_design]

• set_max_transition limits the slew, in ns. A limit on a whole design applies to every pin in it. A limit on a port applies to that port.
• set_max_capacitance limits the load that a driver may see, in pF. The driver can be a cell output or an input port.
• set_max_fanout limits how many loads a driver may drive.

There is a minimum version of each command (set_min_capacitance and so on), but the maximum ones are the ones used in practice.

Limits on Ports

A limit on a port is the easiest way to describe a requirement of the outside world. For example, the chip that receives the output z may require an edge that is faster than 0.5 ns. Put a load on the port, as described in the article about the environment of the ports, and add the limit:

set_load 0.05 [get_ports z]
set_max_transition 0.5 [get_ports z]
report_check_types -max_slew -violators -digits 4

max slew

Pin                                      Limit      Slew     Slack
------------------------------------------------------------------
z                                       0.5000    0.7542   -0.2542 (VIOLATED)

The OR gate that drives z with a load of 0.05 pF makes an edge of 0.7542 ns, and the limit of 0.5 ns is violated by 0.2542 ns. The remedy is a stronger driver, a lower load, or a buffer in front of the output.

For capacitance on an input port, the limit is how much load the port may see. In the demo circuit, the input a drives two cells and has a load of 0.0033 pF. If the outside driver can only handle 0.002 pF, the check shows it:

set_max_capacitance 0.002 [get_ports a]
report_check_types -max_capacitance -violators -digits 4

max capacitance

Pin                                      Limit       Cap     Slack
------------------------------------------------------------------
a                                       0.0020    0.0033   -0.0013 (VIOLATED)

The slack is the limit minus the actual value, so it is -0.0013 pF here, and the unit is pF, not ns.

Limits for the Whole Design

A limit on [current_design] applies to every pin that does not have its own limit. Cells also have limits in the library, and the report prints the one that applies to each pin in the column Limit. With a design limit of 0.05 ns, five pins of the demo circuit violate it, as the article about design rule checks shows. Without any limit in the SDC file, the checks still run with the library limits. In the sky130 library, for instance, the output _4_/X of the XOR gate has a maximum capacitance of 0.0769 pF and a maximum slew of 1.4949 ns.

The Fanout Check

The fanout of a driver is not the number of pins that it drives. It is the sum of the fanout loads of those pins, which come from the library: every input pin can have a fanout_load value, and the library has a default_fanout_load. The sky130 library that this tutorial uses has no fanout loads, and its default is zero. Therefore every net has a fanout of 0, and the check cannot fail:

max fanout

Pin                                   Limit Fanout  Slack
---------------------------------------------------------
a                                         1      0      1 (MET)

With set_max_fanout 1, even the net r1 with two loads has a fanout of 0. The command set_fanout_load, which sets a fanout load on a port, is not supported by OpenSTA. In a real flow with a library that has fanout loads, the check works, but many teams use the capacitance and transition limits instead because they describe the physical effect more directly. Keep this in mind when you see a fanout check that never reports anything.

Reading the Report

The command report_check_types accepts the options -max_slew, -max_capacitance and -max_fanout, and the option -violators to show only the failing pins. In ChipVerify Lab you can add it at the end of the constraint file, because the commands of that file are run when STA reads it. The slack of each line is the limit minus the actual value. A negative number is a violation, whatever the unit.

Common Mistakes

report_check_types -max_slew -violators -digits 4