The slew of a signal, how slowly it rises or falls, is as important as its delay. Every cell uses the input slew to look up its delay and produces a new slew at its output, so a slew travels along a path just like the arrival time. This article follows a slew through a design, shows what happens when two paths meet in a gate, and explains why the slew of one path can change the timing of another.
Think of a door. A door that swings open quickly lets the next person react quickly, and a door that opens slowly makes them wait. In a chip, the slew is how fast a signal changes. A slow change at one point slows down the next gate, and the one after it.
8 min read | Intermediate
What You'll Learn
- Follow a slew along a path through cells and wires
- Explain what slew merging is and why the tool keeps the worst slew for setup
- Show with a lab run how a slow input changes a different path
- Say why hold analysis uses the best slew
Slew Along a Path
You saw in the library chapter that a delay table has two inputs: the input slew and the output load. The same cell has a second set of tables that give the output slew from the same two inputs. A slow input and a heavy load both give a slow output.
The path therefore alternates between two quantities. A cell takes an input slew and a load and gives a delay and an output slew. A wire takes the slew at its start and gives a slightly worse slew at the load pin. The slew leaving one stage is the input of the next:
In the diagram, the flip-flop output has a slew of 0.0787 ns and the wire turns it into 0.0908 ns at the pin of the XOR gate. The XOR gate then looks up its delay with 0.0908 ns, and its output slew is 0.0474 ns, which goes into the setup lookup of the capturing flip-flop.
Where Paths Meet
A gate with two inputs is reached by two different paths. Each of them arrives with its own slew, so the gate has two possible answers for the slew at its output. The tool must decide which one to keep for the next stage, because the next stage has only one input slew per edge.
The usual rule is called slew merging, and it is pessimistic: for setup analysis, the tool keeps the worst, which means the largest, slew of all the arcs that lead to the output. This choice is safe, because in most cases a slower slew does not make the later cells faster. The cost is that a path can be slowed down by a slew that came from a different path. A tool can also keep the slew of the arc with the worst arrival time. That slew is exact for the path through that arc, and optimistic for a path with a slower slew, so the worst-slew rule is the usual default.
One Slow Input Changes Another Path
The XOR gate _4_ in the demo circuit has two inputs. One comes from the flip-flop _7_, and the other from the input port c. Normally both arrive with a slew of 0 or a small value. Now give the port c a very slow edge of 1.0 ns, as an outside driver with a weak output could do:
set_input_transition 1.0 [get_ports c]
Look first at the path that really starts at c. Its slow input now makes the XOR gate much slower, 0.3816 ns instead of 0.1176 ns, and the slack at the flip-flop drops from 1.3650 to 1.0500 ns. That is expected.
The surprise is the path from the flip-flop _7_. Its own signals are unchanged, and the delay of the XOR gate for this path is still 0.1450 ns. But the slew at the output of the XOR gate is now the merged one, 0.1527 ns, which comes from the slow edge of c. The report of the register-to-register path shows it:
Slew Delay Time Description
0.0401 0.2874 0.2874 v _7_/Q (sky130_fd_sc_hd__dfxtp_1)
0.1527 0.1450 0.4323 v _4_/X (sky130_fd_sc_hd__xor2_1)
0.1527 0.0000 0.4323 v _6_/D (sky130_fd_sc_hd__dfxtp_1)
-0.1684 1.8316 library setup time
1.3992 slack (MET)
The slew at the pin _6_/D was 0.0367 ns before, and the library setup time was 0.1174 ns. The larger slew increases the setup time to 0.1684 ns, so the slack falls from 1.4502 to 1.3992 ns, and no signal on this path has changed. The path is slowed down by a slew that does not belong to it. That is the price of merging.
Hold Uses the Best Slew
For a hold check, the logic is the reverse. A hold violation happens when data arrives too early, so the pessimistic view is that of the fastest data. The tool therefore keeps the best, the smallest, slew when it merges for hold analysis. In the example, the hold path through the XOR gate still has a slew of 0.0321 ns, and the hold slack is unchanged at 0.4241 ns. One circuit can have different slews at the same pin, one for setup and one for hold.
Reducing the Pessimism
Merging every slew into the worst one is simple and fast. It is called graph-based analysis, because the tool works on the timing graph with one value per pin. Most of the time the result is only a little pessimistic. When it is too pessimistic, a tool can repeat the calculation for the single path of interest, with the slews that belong to this path only. This is called path-based analysis. It is slower, so it is used on the paths that fail, as a last check.
Common Mistakes
Mistake #1: Looking only at the cell delay in a path report
A path can have a small cell delay and still be slow, because a bad slew at the endpoint raises the setup time. Look at the slew column as well, and see where a large slew was first introduced.
Mistake #2: Setting a slow input transition only on the ports that matter for one path
A slew set on a port can spread into other paths that share a gate with it. If a report looks worse than expected, check the input transitions of the ports that feed the gates on the path.
Quick Check: Why does the tool use the largest slew for setup and the smallest for hold?
Setup is checked with the slowest data, and a larger slew makes the cells slower and the setup time longer. Hold is checked with the fastest data, and a smaller slew makes it faster. Each choice is the pessimistic one for its check.
Practice Exercise
Challenge: Slow Down One Input
Run the sta_demo design with a period of 2.0 ns and note the setup slack of the path from _7_ to _6_ (1.4502 ns) and of the path from the input c to _6_ (1.3650 ns). Add this line to constraints.sdc and run again:
set_input_transition 1.0 [get_ports c]
Predict which of the two slacks changes more, and whether the hold slack of the path from _7_ changes.
Open the ready-made example in the lab, run synthesis, and then run STA. Editing constraints.sdc and re-running only STA, and choosing another library or corner, are PRO features.
Hint
The path from c has the slow input itself. The path from _7_ sees only the merged output slew of the gate.
Solution
The path from c changes much more, from 1.3650 to 1.0500 ns, because the delay of the XOR gate grows from 0.1176 to 0.3816 ns. The path from _7_ still changes, from 1.4502 to 1.3992 ns, because the slew at _6_/D grows to 0.1527 ns and the setup time to 0.1684 ns. The hold slack of that path stays at 0.4241 ns, because hold uses the best slew.
Summary
- Slew travels along a path: a cell turns an input slew and a load into an output slew, and a wire makes the slew worse.
- The slew at an endpoint matters, because it sets the setup and hold time of the capturing flip-flop.
- When paths meet in a gate, setup analysis keeps the worst slew and hold analysis keeps the best slew.
- Merging can make a path slower because of a slew from another path, which adds some pessimism.
- Path-based analysis removes this pessimism for single paths, at the cost of run time.
