Case Analysis and Functional Modes

A chip has several modes: normal operation, test, low power, and others. In each mode some signals are fixed, such as a test enable that is 0 in normal operation. STA does not know that. It assumes that every input can change at any time, and it checks paths that exist only in other modes. Case analysis tells STA that a pin has a constant value in the mode that you are analyzing. STA then follows that constant through the logic and removes the paths that cannot be active. This article shows how the commands work, and what they change in the reports.

8 min read | Intermediate

What You'll Learn

• Explain what case analysis is and why modes need it
• Use set_case_analysis and set_logic_zero / set_logic_one
• Follow a constant through a gate and say which paths disappear
• Use case analysis to analyze one mode at a time

Why Modes Matter

A design with a test mode has a pin that switches between normal operation and test. In normal operation the pin is 0, and the logic that belongs to the test is idle. A path that runs through a multiplexer from a test flip-flop to the data pin of a normal flip-flop is a legal path in the netlist, but in normal operation, the multiplexer never selects it.

If you leave out the mode, STA checks both modes at the same time, and the report contains paths that do not exist in either of them: a path from a test flip-flop to a normal one, through a multiplexer that is never in a state where this path is open. The result is pessimistic. Case analysis fixes the mode.

The Commands

There are two forms. The first one is the most common:

set_case_analysis 0 [get_ports b]
set_logic_one [get_ports d]

• set_case_analysis takes a value, 0 or 1, and a port or pin. The value is a constant during the analysis. The pin can also be internal.
• set_logic_zero and set_logic_one do the same for a pin that is tied to a constant in the design, such as an unused input.

How a Constant Spreads

STA propagates the constant forward through the logic. A gate output becomes constant when the constant at an input decides its value, whatever the other inputs are:

• An AND gate with an input at 0 has an output of 0.
• An OR gate with an input at 1 has an output of 1.
• An inverter, a buffer or a multiplexer with a constant select passes the constant, or the selected input.

A pin with a constant value cannot change, so no transition goes through it, and STA does not time paths through it. The demo circuit shows two cases:

With set_case_analysis 0 [get_ports b], the AND gate that makes the data of the flip-flop _7_ has an input at 0, so its output is always 0. The flip-flop _7_ then has a constant at its data pin and no path ends there. The setup summary no longer lists _7_/D:

max_delay/setup group clk

Endpoint                                 Delay     Delay     Slack
z (output)                              1.6000    0.5674    1.0326 (MET)
y (output)                              1.6000    0.3956    1.2044 (MET)
_6_/D (sky130_fd_sc_hd__dfxtp_1)        1.8826    0.5176    1.3650 (MET)

With set_logic_one [get_ports d], the OR gate that makes the output z is always 1. No transition reaches z, so z disappears from the list. The other endpoints stay.

Analyzing One Mode at a Time

The usual use is to run STA once for each mode and to set the mode pins with case analysis:

# normal mode
set_case_analysis 0 [get_ports test_mode]

# test mode
set_case_analysis 1 [get_ports test_mode]

The constraints of the two runs differ only in these lines. A clock multiplexer works in the same way: set_case_analysis 1 [get_ports sel] keeps only the clock that the multiplexer selects, as the article about clock muxes showed.

Case Analysis Compared With a False Path

A false path says that a path is not interesting. Case analysis says why: a pin has a fixed value. The two give a similar result, but case analysis is safer in two ways. It does not need a list of paths, because the constant finds them by itself, so a new path that goes through the same logic is removed too. And it is a statement about the mode, which can be checked against the test logic. For these reasons, use case analysis when the reason is a constant, and a false path only when there is no constant.

Common Mistakes

set_case_analysis 0 [get_ports b]