On-Chip Variation and Timing Derates

A corner describes the whole chip at one condition. But two cells on the same chip, next to each other, are not exactly equal. One may be a little faster than the other because of small differences in manufacturing, in the local voltage and in the local temperature. This is on-chip variation, OCV. It matters most for a path whose launch clock and capture clock go through different cells, because one can be slow and the other fast in the same chip. STA covers this with derates. This article explains what a derate is, how early and late are used for setup and hold, and shows the effect on a real clock tree.

9 min read | Intermediate

What You'll Learn

• Explain what on-chip variation is and how it differs from a corner
• Use set_timing_derate with -early and -late
• Say which paths are made slower and which faster for the setup check and for the hold check
• Calculate the slack of a path with derates by hand

Corners and On-Chip Variation

A corner is a global condition: every cell of the chip is at the same process, voltage and temperature. On-chip variation is a local difference inside one chip. For the launch flip-flop and the capture flip-flop of a path, the corner says that both are slow, or both are fast. OCV says that, within the same corner, one of them can still be a few percent slower than the other. A check that ignores this is optimistic, because the worst case is that the launch path is as slow as it can be while the capture path is as fast as it can be.

The Derate

A derate is a factor that STA applies to the delays to cover the variation. There are two values:

• -late is the factor for delays that should be larger than normal, for example 1.1, which is 10 percent more.
• -early is the factor for delays that should be smaller than normal, for example 0.9, which is 10 percent less.

set_timing_derate -early 0.9
set_timing_derate -late 1.1

The derates apply to cell delays and, if you do not choose otherwise, to net delays as well. The options -cell_delay and -net_delay select one of them, and -clock and -data select the clock paths or the data paths. Library setup and hold times are not changed by these derates. They can be derated separately with the option -cell_check.

Which Is Used Where

For each check, STA makes the situation worse for the design on purpose. The rule is simple: the path that makes the check harder gets the worse factor.

For setup, a slow launch and a slow data path make the data late, and a fast capture clock makes the deadline early. For hold, the data is as early as possible and the capture clock is as late as possible. These are the worst cases for the two checks.

A Clock Tree Example

Take the clock tree of the article about clock latency. The clock goes through a root buffer to both flip-flops, and through more buffers to the capture flip-flop. With propagated clocks and the two derates above, the setup check has these numbers:

• The launch clock path is late: it needs 0.1871 ns instead of 0.1701 ns to reach r1.
• The clock-to-Q delay is late: 0.3097 ns instead of 0.2815 ns. The data arrives at 0.1871 + 0.3097 = 0.4968 ns.
• The capture clock path is early: 0.2191 ns instead of 0.2435 ns, so the capture edge is at 2.2191 ns instead of 2.2435 ns.

The required time is 2.2191 + 0.0202 - 0.1029 = 2.1364 ns. The term 0.0202 ns is a credit that is explained in Common Path Pessimism Removal. The slack is 2.1364 - 0.4968 = 1.6396 ns, compared with 1.6889 ns without derates. For hold, the picture is the opposite:

The launch path is early (0.1531 ns), the clock-to-Q delay is early (0.2590 ns) and the data arrives at 0.4121 ns. The capture clock is late (0.2678 ns). The required time is 0.2678 - 0.0202 - 0.0300 = 0.2176 ns, and the hold slack is 0.4121 - 0.2176 = 0.1945 ns, compared with 0.2444 ns without derates.

Derates Without a Clock Tree

With ideal clocks, there are no clock cells, and the derates only work on the data path. In the demo circuit, the setup slack of the path from _7_ to _6_ goes from 1.4502 ns to 1.4070 ns, and the hold slack from 0.4241 ns to 0.3875 ns. The arrival time at 0.4756 ns is the sum of the late clock-to-Q delay (0.3161 ns) and the late XOR delay (0.1595 ns). The setup time of 0.1174 ns is the same as before.

Choosing the Values

The size of the derates comes from the technology and from the foundry. Values of a few percent are common for the newer technologies, and larger for older ones or for conservative flows. A flat derate is simple, but it treats a path of two cells in the same way as a path of twenty cells, and a single large derate is pessimistic for the long ones. The next articles describe methods that take the depth of the path into account.

Common Mistakes

set_timing_derate -early 0.9
set_timing_derate -late 1.1