Disabling Arcs and Breaking Loops

STA computes arrival times by walking through the timing graph from the startpoints to the endpoints. This only works if the graph has no cycles. A combinational loop, where the output of a gate eventually feeds its own input, is a cycle, and the walk would never end. Real designs contain such loops in a few cases, and designers also sometimes want to remove a timing arc on purpose. This article shows how STA deals with loops, and how set_disable_timing removes an arc.

8 min read | Intermediate

What You'll Learn

• Explain why a combinational loop is a problem for STA
• Read the loop warning of check_setup and the list of disabled edges
• Use set_disable_timing to disable an arc or a whole cell
• Know when an arc should be disabled and when not

Combinational Loops

A combinational loop is a ring of gates with no flip-flop in it. The classic example is a latch made of two cross-coupled NOR gates. The output of the first gate goes into the second one, and the output of the second one goes back into the first:

Arrival times are defined by adding delays along a path. In a loop, the path never ends, because you can go round it again and again. STA breaks every loop by cutting one arc, so that the graph has no cycles. It does so automatically and prints a warning. This is the output of check_setup -verbose for the design above:

Warning: There is 1 combinational loop in the design.
  n2/Y
  n1/B
  n1/Y
  n2/B
  | loop cut point
  n2/Y

The list shows the pins of the loop in order, and the line loop cut point marks where STA cut it, at the output n2/Y. The command report_disabled_edges lists the arcs that are not used in the timing. Here it shows the arc that STA has cut:

n2 B Y loop

The line says that the arc from the pin B to the pin Y of the cell n2 is disabled because of the loop. The arc from A to Y of the same cell is still timed. The paths through the loop are still found: the path from the input s through n2 and n1 to the data pin of the flip-flop is checked, and it has a slack of 1.3620 ns.

Why Cutting Is a Choice

Which arc STA cuts decides which paths are timed. A different cut point times a different set of paths, and the same circuit can give different numbers. For this reason, a loop in a design that has to be signed off should not be left to the tool. A designer who knows which arc of the loop is not used in practice can disable it, and the tool then uses that arc as the cut. The loop should also be understood: it may be intended, as in a latch built from gates, or it may be a design mistake.

Disabling an Arc

The command set_disable_timing removes arcs from the timing graph:

set_disable_timing -from B -to Y [get_cells n2]
set_disable_timing [get_cells n2]
set_disable_timing [get_ports test_in]

• With -from and -to on a cell, it disables one arc of that cell. The names are the pins of the cell.
• With only a cell, it disables all the arcs of the cell.
• With a port or a pin, it disables the timing through that point.

After the first command, the list of disabled edges shows the reason of the arc as both the constraint and the loop:

n2 B Y constraint, loop

It is the same arc that STA had cut. Now the cut is a decision of the designer. The loop warning still appears, because the loop is still in the netlist, but its cut point is the one that you chose.

Other Uses

• An arc that never carries data in the real circuit, such as the arc through a test multiplexer that is only used in a test mode. Case analysis is better when the reason is a constant, as in the article about case analysis.
• An arc inside a macro or a library cell that is not used in your application.

Disabling Compared With a False Path

A false path removes the paths between named points. A disabled arc removes a piece of the graph, so every path that uses the arc is gone, whatever its start and end. It has a bigger effect and is harder to see in the reports, as a disabled arc leaves no message when the paths vanish. Use it for a specific, understood arc, and write the reason in a comment.

Common Mistakes

module sta_loop (clk, s, r, q);
  input clk; input s; input r; output q;
  wire a, b;
  sky130_fd_sc_hd__nor2_1 n1 (.A(r), .B(b), .Y(a));
  sky130_fd_sc_hd__nor2_1 n2 (.A(s), .B(a), .Y(b));
  sky130_fd_sc_hd__dfxtp_1 f (.CLK(clk), .D(a), .Q(q));
endmodule