Debugging a Failing Path from the Report

A timing report that ends with a negative slack is not a failure of the tool, it is a message about the design. The skill is to read it: which check failed, which cells take the time, and what kind of change would remove the time. This article takes the UART transmitter of the previous article, runs it with a faster clock, and debugs the two violations that appear, step by step, using only what the report prints.

10 min read | Intermediate

What You'll Learn

• Follow a five-step routine from a violated slack to a decision about the fix
• Read the Cap, Slew and Delay columns to find the cells that cost the most time
• Tell a slow cell from a slow load and choose the matching change
• Explain a removal violation on an asynchronous reset

The Situation

The UART from the previous article met timing at 10 ns with a wide margin. Now the target is a clock period of 3.4 ns (about 294 MHz) at the slow corner (the library for 100 C and 1.60 V), with an input delay and an output delay of 0.5 ns. The setup of the SDC is the same as before, only the numbers change:

create_clock -name clk -period 3.4 [get_ports clk]
set_input_delay 0.5 -clock clk [get_ports {rst_n start data*}]
set_output_delay 0.5 -clock clk [get_ports {tx busy}]

Without PRO you can see the same two violations at the typical corner, with a period of 1.7 ns and an input delay of 0.2 ns on rst_n: the setup slack is -0.0523 ns and the removal slack is -0.0956 ns. The rest of this article uses the slow corner.

The summary commands report worst slack max -0.32 and tns max -2.42. The first number is the worst violation, and the second is the sum of all the violations. If the total is much larger than the worst slack, many endpoints fail. Here the total is about eight times the worst slack, so there is a group of failing endpoints, not one.

A Five-Step Routine

1. Find which check failed: setup or hold, and in which path group.
2. Read the start point and the end point. Do they belong to the same clock?
3. Find the cells with the largest delay on the path.
4. For each of them, look at the load (Cap) and the slew, to see why it is slow.
5. Choose the change that removes the cause, and estimate the new slack before you try it.

Step 1 and 2: Which Check, Which Path

The first violation is in the group clk, which is a setup check of a path from a flip-flop to a flip-flop, both clocked by clk. The start point is _150_, which is the flip-flop for bit 4 of the baud counter (cnt[4]), and the end point is _133_, which is the bit 0 of the shift register (shreg[0]). A path from the counter to the shift register is the path through the compare cnt == 867: when the counter reaches 867, the tick moves the shift register.

Step 3: The Cells That Cost the Most

The report with the load and slew columns added (-fields {cap slew}) is:

      Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------
             0.0000    0.0000    0.0000   clock clk (rise edge)
                       0.0000    0.0000   clock network delay (ideal)
             0.0000    0.0000    0.0000 ^ _150_/CLK (sky130_fd_sc_hd__dfrtp_1)
   0.0106    0.1459    0.7761    0.7761 v _150_/Q (sky130_fd_sc_hd__dfrtp_1)
   0.0076    0.3149    0.5085    1.2847 v _070_/Y (sky130_fd_sc_hd__nand4bb_1)
   0.0045    0.1613    0.9147    2.1994 v _072_/X (sky130_fd_sc_hd__or3_1)
   0.0174    0.9183    0.8244    3.0237 ^ _105_/Y (sky130_fd_sc_hd__nor3_1)
   0.0019    0.0837    0.5440    3.5677 ^ _121_/X (sky130_fd_sc_hd__a221o_1)
             0.0837    0.0000    3.5677 ^ _133_/D (sky130_fd_sc_hd__dfrtp_1)
                                 3.5677   data arrival time

             0.0000    3.4000    3.4000   clock clk (rise edge)
                       0.0000    3.4000   clock network delay (ideal)
                       0.0000    3.4000   clock reconvergence pessimism
                                 3.4000 ^ _133_/CLK (sky130_fd_sc_hd__dfrtp_1)
                      -0.1487    3.2513   library setup time
                                 3.2513   data required time
-------------------------------------------------------------------------------
                                 3.2513   data required time
                                -3.5677   data arrival time
-------------------------------------------------------------------------------
                                -0.3165   slack (VIOLATED)

Put the same data on a waveform. The data leaves the counter flop at the clock edge at 0, and every cell adds its delay. The result arrives at 3.5677 ns, which is after the capture flop needs it:

The path has five cells, and the biggest delays are the or3 cell (0.9147 ns), the nor3 cell (0.8244 ns) and the flip-flop itself (0.7761 ns). The three of them are 2.5 ns of the 3.5677 ns. Slack = 3.2513 - 3.5677 = -0.3165 ns.

Step 4: Why Is Each Cell Slow?

Look at the Cap and Slew columns of the two slow cells:

The two cells need different cures, as the article about optimization techniques explained. A bigger or3 would not help, because its load is already small, and its delay is mostly its own internal stages. It needs a different structure. The nor3 has three transistors in series on its rising output, which makes it weak, and it is driving 0.0174 pF, four times the load of the or3. A stronger cell or a buffer in front of the load would reduce its delay and its slew. The large slew also hurts the next cell: the a221o after it takes 0.5440 ns.

The flip-flop delay of 0.7761 ns is not a cell you can improve. It is the clock-to-Q delay of the cell with the load that it has.

Step 5: Choose and Estimate

The slack is -0.3165 ns, so the change has to remove at least 0.32 ns from this path (and from the other failing endpoints, which are similar). The list of options and their rough effect:

• Make the nor3 stronger. It could save a part of its 0.8244 ns, perhaps 0.2 to 0.3 ns, and it adds load to the or3 before it. It is a local change that the synthesis tool can do.
• Reduce the number of cells. The compare of a 10-bit counter with 867 is a wide AND of 10 bits, and it is in series with the logic that uses it. The path has 5 cells for a few bits of logic.
• Move the compare out of the path. If the result of the compare is stored in a flip-flop (a registered tick), the path to shreg starts at that flip-flop and has no compare in it. The compare gets its own full clock period.

The last option removes the most delay and does not rely on the size of a single cell. It changes the design, and the article at the end of this chapter does it and measures the result.

The Second Violation: Removal

The report also shows a failure in the path group asynchronous, which is a different kind of check. It is a hold-type check, so it is printed in the min report:

Startpoint: rst_n (input port clocked by clk)
Endpoint: _133_ (removal check against rising-edge clock clk)
Path Group: asynchronous
Path Type: min

    Delay      Time   Description
-------------------------------------------------------------
   0.0000    0.0000   clock clk (rise edge)
   0.0000    0.0000   clock network delay (ideal)
   0.5000    0.5000 ^ input external delay
   0.0000    0.5000 ^ rst_n (in)
   0.0000    0.5000 ^ _133_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
             0.5000   data arrival time

   0.0000    0.0000   clock clk (rise edge)
   0.0000    0.0000   clock network delay (ideal)
   0.0000    0.0000   clock reconvergence pessimism
             0.0000 ^ _133_/CLK (sky130_fd_sc_hd__dfrtp_1)
   0.6148    0.6148   library removal time
             0.6148   data required time
-------------------------------------------------------------
             0.6148   data required time
            -0.5000   data arrival time
-------------------------------------------------------------
            -0.1148   slack (VIOLATED)

The removal check says that when the reset is released (the rising edge of rst_n), it must not be released too close to a clock edge. The flip-flop needs the reset to stay active until 0.6148 ns after the clock edge. Here the reset port is connected directly to the reset pin, so the arrival time is just the input delay, 0.5000 ns, and that is 0.1148 ns too early.

In this path there is no cell to resize, because the reset has nothing between the port and the pin. The cure is in the design: the release of the reset must be made synchronous, which means it must come from a flip-flop clocked by clk, so that it changes shortly after the clock edge and has a whole period to settle before the next. This is the reset synchronizer of the last article of this chapter. Adding delay to the reset path would also fix this particular number, but the delay would have to be found separately for every corner, and it hides the real problem, which is that the release of the reset is not related to the clock.

Results at the Three Corners

Run the same design with the same 3.4 ns constraints at the three corners of the library. The worst setup slack and the worst removal slack are:

The design passes with a good margin at the typical and fast corners, and it fails at the slow one. A violation that only shows at one corner, as here, is typical for setup in the slow library. The removal check fails at the slow corner, because the removal time of the flip-flop is longer there, 0.6148 ns.

Common Mistakes