PVT Corners and STA

A corner is one combination of these conditions. STA does not guess which one the chip will meet. It checks the design at the corners that give the worst result for each check. This article explains the three conditions, shows the numbers of the demo circuit at three corners, and explains why setup and hold are checked at different corners.

8 min read | Intermediate

What You'll Learn

• Name the three conditions that define a PVT corner
• Explain which corner is worst for setup and which one for hold
• Run STA with several libraries at once and read the combined result
• Say why checking only the typical corner is not enough

Process, Voltage, Temperature

PVT stands for three things that change the speed of every cell:

• Process: small differences in the manufacturing, such as the thickness of a layer. Some chips come out fast and some come out slow.
• Voltage: the supply voltage is not exactly the same everywhere or all the time. A lower voltage makes the cells slower.
• Temperature: the chip is cold when it starts and hot when it runs a heavy load. For many technologies, a higher temperature makes the cells slower.

The library vendor characterizes the cells at a few selected combinations, and delivers one library file for each. The article about library characterization explains how the numbers are made. For sky130 these are three corners:

Which Corner for Which Check

Setup fails when the data is too slow. The risk is highest when the cells are slowest, so setup is checked at the slow corner. Hold fails when the data is too fast, and the risk is highest when the cells are fastest, so hold is checked at the fast corner. These are the worst slacks of the demo circuit at the three corners, with a clock of 2.0 ns:

The setup slack gets smaller towards the slow corner, from 1.0994 ns to 0.7856 ns, and the hold slack gets smaller towards the fast corner, from 0.5966 ns to 0.2681 ns. If you only had the typical corner, you would see 1.0326 ns and 0.4241 ns, and both numbers are better than the worst case.

Running Several Corners at Once

OpenSTA can read more than one library in one run, one for each corner. You define the corners first, and then read each library into its corner:

define_corners ss tt ff
read_liberty -corner ss sky130_fd_sc_hd__ss_100C_1v60.lib
read_liberty -corner tt sky130_fd_sc_hd__tt_025C_1v80.lib
read_liberty -corner ff sky130_fd_sc_hd__ff_n40C_1v95.lib
read_verilog netlist.v
link_design sta_demo
read_sdc constraints.sdc

After that, report_checks -corner ss reports one corner. Without the option, the report takes the worst result over all corners for each check, so that you do not have to pick the corner yourself:

worst slack max 0.7856
worst slack min 0.2681

The worst setup slack of 0.7856 ns comes from the slow corner and the worst hold slack of 0.2681 ns from the fast corner. These are the same numbers as in the table. Note also that the worst setup endpoint changes with the corner: at the typical corner it is the output z (1.0326 ns), but at the slow corner the output y (0.7856 ns) is worse. A path that is not critical in one corner can be critical in another, because the cells do not all scale by the same factor.

Why Not Only the Typical Corner

The typical corner describes an average chip. Half of the chips that you make are worse than that. A design that has a positive slack only at the typical corner works on some chips and fails on others, and you find out in the lab or at the customer. Signing off at the worst corner for each check means that the design is correct for the whole range of the conditions that the corners describe.

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