Fixing Hold Violations

A hold violation means the new data arrives too early. The main way to fix it is the opposite of a setup fix: make the data path slower. This article shows a real hold violation, the fix that tools use, the price of that fix, and the order in which a design flow handles hold.

8 min read | Intermediate

What You'll Learn

• Recognize which paths are likely to violate hold
• Explain how adding a delay cell fixes a hold violation
• Say what a hold fix costs in setup slack, area and power
• Explain why hold is fixed late in the design flow and why it cannot be fixed by the clock period

Where Hold Violations Appear

The hold check asks whether the new data is late enough. It fails when the data path is very fast, or when the capture clock is late. The paths most at risk are:

• A flip-flop that feeds another flip-flop directly, with no logic in between. The only delay is the clock-to-Q delay of the first flip-flop.
• Paths where the capture flip-flop receives its clock later than the launch flip-flop.
• Paths checked at the fast corner of the library, where all cells are at their quickest.

A Real Hold Violation

Take two flip-flops connected directly, a 2.0 ns clock, and a capture clock that arrives 0.4 ns later than the launch clock, as can happen in a real clock tree:

create_clock -name clk -period 2.0 [get_ports clk]
set_input_delay  0.4 -clock clk [get_ports d]
set_output_delay 0.4 -clock clk [get_ports q]
set_clock_latency 0.4 [get_pins r2/CLK]

The new data leaves the first flip-flop at the launch edge, and needs 0.2749 ns to reach the second one. The second flip-flop needs the old data until 0.4 - 0.0346 = 0.3654 ns. The data comes 0.0904 ns too early:

   0.0000    0.0000    0.0000 ^ r1/CLK (sky130_fd_sc_hd__dfxtp_1)
   0.0017    0.0329    0.2749    0.2749 ^ r1/Q (sky130_fd_sc_hd__dfxtp_1)
             0.0329    0.0000    0.2749 ^ r2/D (sky130_fd_sc_hd__dfxtp_1)
                                 0.2749   data arrival time

   0.0000    0.0000    0.0000   clock clk (rise edge)
             0.4000    0.4000   clock network delay (ideal)
             0.4000 ^ r2/CLK (sky130_fd_sc_hd__dfxtp_1)
  -0.0346    0.3654   library hold time
             0.3654   data required time
            -0.2749   data arrival time
            -0.0904   slack (VIOLATED)

The Fix: Delay the Data

The data must arrive at least 0.0904 ns later. The usual way is to put a delay cell, or a chain of buffers, into the data path. A delay cell is a cell that does nothing except take time. The sky130 library has a family of them. A cell called dlygate4sd3_1 adds 0.5205 ns in this path:

The diagram shows the two clocks, with the capture clock 0.4 ns later, and the data pin of the capture flip-flop before and after the fix. Before the fix, the new data arrives before the red line, which is the required time. After the fix, it arrives at 0.7958 ns, long after the line. The report now says:

   0.0017    0.0333    0.2753    0.2753 ^ r1/Q (sky130_fd_sc_hd__dfxtp_1)
   0.0017    0.0451    0.5205    0.7958 ^ dly1/X (sky130_fd_sc_hd__dlygate4sd3_1)
             0.0451    0.0000    0.7958 ^ r2/D (sky130_fd_sc_hd__dfxtp_1)
                                 0.7958   data arrival time
                                 0.3628   data required time
                                 0.4330   slack (MET)

The hold slack is now +0.4330 ns. That is more than needed, because this particular cell is large. A tool chooses the smallest delay that is enough, and it can use a smaller cell or a chain of small buffers.

What a Hold Fix Costs

The delay cell sits in the data path, so it also delays the data for the setup check. In the same design, the setup slack of this path falls from 2.0200 ns to 1.4801 ns. A hold fix is therefore only possible if the setup slack of the path can pay for it. If a path has a hold violation and almost no setup slack, the clock tree itself must be changed instead. A hold fix also adds cells, so it costs area and power. A design with thousands of short paths can need thousands of delay cells.

Other Ways to Fix Hold

• Change the clock arrival times. An earlier capture clock, or a later launch clock, gives more hold slack. This is the useful skew from the article about skew used in the other direction.
• Use a slower version of a cell on the data path. It fixes the path without adding a cell.

The clock period cannot help. The hold slack stays the same whether the clock runs at 10 ns or at 1 ns.

When Hold Is Fixed

Hold fixing is done late. The reason is that the skew between flip-flops only becomes known when the clock tree is built. Fixing hold before that would waste cells on violations that may not exist, or miss the ones that do. The flow is: first make setup pass, then build the clock tree, then fix hold on the real clock arrival times, and then check setup again. At sign-off, hold is checked at the fast corner of the library, because the fast corner has the shortest delays.

Common Mistakes

set_clock_latency 0.5 [get_pins _6_/CLK]