Clock Skew: Useful and Harmful

Clock skew is the difference between the times at which a clock edge reaches two flip-flops. It sounds like a defect, and it can be one. But skew also moves time from one path to the next, and designers sometimes use that on purpose. This article shows what skew does to the setup and hold checks, when it is harmful, and when it is useful, with the numbers of a real design.

8 min read | Intermediate

What You'll Learn

• Define clock skew and say why it is never exactly zero in a real chip
• Predict the effect of skew on the setup and hold slack of a path
• Explain why a change of skew helps one path and hurts its neighbours
• Describe useful skew and the conditions under which it is safe

What Skew Is

A clock starts at one source, such as an input pin of the chip, and reaches thousands of flip-flops through wires and buffers. The route to each flip-flop has a slightly different length and load, so the clock edge arrives at different times. The arrival time at a flip-flop is its clock latency. For two flip-flops that exchange data, the skew is:

Skew = Tcapture - Tlaunch

Here Tlaunch is the clock latency of the flip-flop that sends the data and Tcapture is the clock latency of the flip-flop that receives it. A positive skew means that the receiving flip-flop gets the clock later. The spread between the earliest and the latest clock arrival over all the flip-flops of a clock tree is also called skew, and it is the number that clock tree synthesis tries to keep small. Before the clock tree exists, STA uses ideal clocks and the skew is zero. After the clock tree is built, the tool follows the real clock paths and skew appears in the reports.

What Skew Does to Setup and Hold

The earlier articles on the setup equation and the hold equation show where the skew enters. For a path from a launch flip-flop to a capture flip-flop:

The reason is the same in both cases. A later capture clock gives the data more time to arrive, which is good for setup. It also means the old data has to stay at the input for longer, which is bad for hold. Skew moves the slack of the two checks in opposite directions by the same amount.

Skew Affects the Neighbours Too

A flip-flop is usually both the capture flip-flop of one path and the launch flip-flop of the next. If you delay its clock, you help the path that ends at it and hurt the path that starts at it. Look at a real example. This is the design, a small logic cone between two flip-flops, followed by an output:

module sta_chain (input clk, input a, b, c, d, e, output q);
  reg r1, r2;
  always @(posedge clk)
    r1 <= a;
  wire w = (((r1 ^ b) & c) ^ (d | e)) & (r1 | d);
  always @(posedge clk)
    r2 <= w;
  assign q = r2;
endmodule

create_clock -name clk -period 1.0 [get_ports clk]
set_input_delay  0.2 -clock clk [get_ports {a b c d e}]
set_output_delay 0.2 -clock clk [get_ports q]

With a 1.0 ns clock, the path from the first flip-flop (_12_ in our run) to the second flip-flop (_11_) has a setup slack of -0.0585 ns: it fails. The path from the second flip-flop to the output q has plenty of spare time, 0.5385 ns. Now delay the clock of the second flip-flop by 0.1 ns:

set_clock_latency 0.1 [get_pins _11_/CLK]

The first path, which ends at the delayed flip-flop, gets 0.1 ns more time for setup and the violation is gone: the slack is now +0.0415 ns. Its hold slack falls by 0.1 ns, from 0.3439 to 0.2439 ns, which is still positive. The second path starts at the delayed flip-flop. Its data leaves 0.1 ns later, so its setup slack falls from 0.5385 to 0.4385 ns, and its hold slack rises from 0.4585 to 0.5585 ns.

Nothing was created or destroyed. The 0.1 ns that the first path gained was taken from the second path, which could afford to lose it. A change of the clock arrival time moves slack between neighbouring paths. It does not add any.

Harmful Skew

Skew is harmful when it takes slack from a path that has none to spare. There are two common cases:

• Hold: a capture clock that arrives late makes the hold check harder. A path with very little logic, such as a flip-flop that feeds another one directly, has little hold slack and is the first to fail.
• Setup: a launch clock that arrives late, or a capture clock that arrives early, reduces the time for a long path.

Clock tree synthesis tries to keep the skew small for this reason, but it can never make it zero. The analysis must always use the real clock arrival times that the tool reports.

Useful Skew

If some paths fail setup and their neighbours have slack to spare, the designer can delay the capture clock of the failing path on purpose. This is called useful skew, and it works like in the example above. The conditions are:

• The neighbouring paths must have enough setup slack to give away.
• Every hold check that gets harder must still pass. Here the hold slack of the first path stayed positive.
• The clock tree must be built so that the delay is real and repeatable. The tool adds it with extra clock buffers.

Useful skew is one of the tools to repair setup violations, and the article Fixing Setup Violations compares it with the other options.

Common Mistakes