Timing-Aware RTL: Pipelining and Retiming

Most of the timing of a chip is decided before any layout exists, in the RTL. An RTL structure that needs too many gates in series between two registers cannot be saved by the tools. A designer who knows what STA reports can write the RTL so that the paths are short. This article explains pipelining and retiming, shows them on an 8-bit adder with real numbers, and gives some coding habits that keep paths short.

9 min read | Intermediate

What You'll Learn

• Explain how the logic depth between registers sets the clock period
• Split a long path with a pipeline register and calculate the new clock limit
• Describe retiming and the balance of pipeline stages
• List the costs of pipelining and some RTL habits for shorter paths

Depth Sets the Clock

The clock period of a design has to cover the longest path between two registers: the clock-to-Q delay, the delays of all the gates in between, and the setup time. The more gates in series, the longer the period. For a given function, the structure that you describe in the RTL decides the number of levels, and synthesis can only reduce it by a limited amount.

An Example: an 8-Bit Adder

Here is an adder that adds two 8-bit numbers that come from registers, and stores the 9-bit result in a register:

module add1 (input clk, input [7:0] a, b, output reg [8:0] s);
  reg [7:0] ra, rb;
  always @(posedge clk) begin
    ra <= a;
    rb <= b;
    s <= ra + rb;
  end
endmodule

The carry has to ripple through the bits, and the path from the registers ra and rb to s is long. With a 1.2 ns clock, the worst setup slack is -1.7458 ns. The path needs about 1.2 + 1.7458 = 2.95 ns, and that is the shortest clock period of this design.

Pipelining

Pipelining puts a register in the middle of a long path, so that each half has a full clock period. In the adder, the low nibble and its carry are added in the first stage, and the high nibble in the second stage:

module add2 (input clk, input [7:0] a, b, output reg [8:0] s);
  reg [7:0] ra, rb;
  reg [4:0] lo; reg [3:0] ha, hb;
  always @(posedge clk) begin
    ra <= a;
    rb <= b;
    lo <= ra[3:0] + rb[3:0];          // stage 1: low nibble and its carry
    ha <= ra[7:4];
    hb <= rb[7:4];
    s <= {ha + hb + lo[4], lo[3:0]};   // stage 2: high nibble
  end
endmodule

The two-stage adder runs at 1.5 ns, and its shortest period is about 1.2 + 0.1921 = 1.39 ns. The clock can be more than twice as fast. The price is paid in other places:

• 13 more flip-flops (5 for the low nibble and its carry, and 8 for the high nibble inputs), which adds area and power.
• One more clock cycle of latency. The result appears one cycle later than before, and the rest of the design must be able to deal with it. This is a change in the behaviour, not only in the timing.
• The control logic and the data that goes with the result must be delayed in the same way, so that they stay aligned.

Balance the Stages

A pipeline is only as fast as its slowest stage. If one stage has 0.40 ns of slack and the other 0.29 ns, as in the pipelined chain design of the earlier articles (stage 1: 0.3995 ns, stage 2: 0.2854 ns at a 1.0 ns clock), the second stage is the limit. Moving a gate from the second stage to the first one makes the slacks equal and lets the clock run faster, or removes a violation of the slower stage.

Retiming does this automatically. It moves registers forward or backward across gates without changing the function seen from the outside. A tool can retime a design to balance the stages, but the registers it moves have a new meaning inside the design: the reset values and the visible signals of the original registers change. Designers use it when the structure is not a matter of function, and keep the registers whose names and reset values are used by software or by the verification environment.

RTL Habits for Short Paths

• Register the outputs of a block, and register the inputs of a block if the previous block is slow. A boundary of registers turns a long path into two short ones.
• Avoid long chains of if and else if when the conditions are exclusive. A case statement describes parallel logic.
• Balance trees: sum or compare many values in a tree, not in a chain.
• Keep large multiplexers and wide comparisons close to registers, or split them over two cycles.
• Do not put a late-arriving signal at the start of the logic. Put it in the last level, where it only has to pass one gate.
• Look at the first synthesis report early. The worst paths show where the structure has to change.

Common Mistakes