Latch Timing and Time Borrowing

A flip-flop takes its data at one instant, the clock edge. A latch is different. While its enable is active it is transparent, which means that its output follows its input. Data that arrives late, after the latch has opened, still goes through. This changes how STA does the arithmetic: the arrival time at a latch does not have to be before the opening edge, and the time that the data takes beyond it is passed on to the next stage. This is called time borrowing. This article explains latches in STA, with the numbers of a real run.

9 min read | Intermediate

What You'll Learn

• Explain how a level-sensitive latch differs from an edge-triggered flip-flop
• Calculate the time borrowed by a latch and its maximum
• Read a latch report: time borrowed, time given to the startpoint
• Explain what happens when the data arrives after the latch has closed

A Latch Is Transparent

A positive level-sensitive latch is transparent while its enable is high. In this design the enable is the clock, so the latch is open from the rising edge at 0 to the falling edge at 1.0 ns, and closed from 1.0 ns to 2.0 ns. While it is open, its output follows its input. When it closes, the output keeps the last value:

The example has a rising-edge flip-flop r1, a delay cell, a latch lat, a buffer, and a second flip-flop r2. The netlist is written by hand with library cells, because the STA flow behind these examples does not map latches from RTL. The latch cell of the library is dlxtp_1.

The Setup Check at a Latch

For a flip-flop, the data must arrive before the edge. For a latch, the data has a window. It can arrive up to the time when the latch closes, minus the setup time of the latch. The check is made against the closing edge. For the latch above:

• The latch opens at 0 and closes at 1.0 ns. The pulse width is 1.0 ns.
• The library setup time of the latch is 0.0465 ns.
• The maximum time that the data may arrive after the opening edge is 1.0 - 0.0465 = 0.9535 ns. This is the maximum time borrow.

Time Borrowing

If the data arrives before the latch opens, nothing is borrowed, and the next stage starts at the opening edge. If it arrives after the opening edge but before the closing limit, the data passes through, and the part after the opening edge is borrowed from the next stage. In the example, the data from r1 arrives at the latch at 0.4780 ns:

Startpoint: r1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: lat (positive level-sensitive latch clocked by clk)

   0.0000    0.0000 ^ r1/CLK (sky130_fd_sc_hd__dfxtp_1)
   0.2682    0.2682 v r1/Q (sky130_fd_sc_hd__dfxtp_1)
   0.2098    0.4780 v dl1/X (sky130_fd_sc_hd__dlygate4sd1_1)
   0.0000    0.4780 v lat/D (sky130_fd_sc_hd__dlxtp_1)
             0.4780   data arrival time

   0.0000    0.0000 ^ lat/GATE (sky130_fd_sc_hd__dlxtp_1)
   0.4780    0.4780   time borrowed from endpoint
             0.4780   data required time
             0.0000   slack (MET)

Time Borrowing Information
clk pulse width                         1.0000
library setup time                     -0.0465
max time borrow                         0.9535
actual time borrow                      0.4780

The row time borrowed from endpoint adds the borrowed time to the opening edge, and the required time becomes equal to the arrival time. The slack of the path is zero, as long as the borrow is within the limit. This is not a problem. The borrowed time is not lost: it shows up in the next path.

Time Given to the Startpoint

The path that starts at the latch now has a late start. STA adds the time that was borrowed to the start of the next path. In the report of the path from the latch to r2, the row is named time given to startpoint:

Startpoint: lat (positive level-sensitive latch clocked by clk)
Endpoint: r2 (rising edge-triggered flip-flop clocked by clk)

   0.0000    0.0000   clock clk (rise edge)
   0.4528    0.4528   time given to startpoint
   0.0000    0.4528 ^ lat/D (sky130_fd_sc_hd__dlxtp_1)
   0.3113    0.7641 ^ lat/Q (sky130_fd_sc_hd__dlxtp_1)
   0.0688    0.8329 ^ b1/X (sky130_fd_sc_hd__buf_1)
   0.0000    0.8329 ^ r2/D (sky130_fd_sc_hd__dfxtp_1)
             0.8329   data arrival time

   2.0000    2.0000   clock clk (rise edge)
  -0.0576    1.9424   library setup time
             1.9424   data required time
             1.1095   slack (MET)

The next stage starts 0.4528 ns after the clock edge (the rising transition is a little faster than the falling one, so the number differs from 0.4780 ns) and then adds the delay of the latch, from D to Q, and the buffer. The slack of the second stage is 1.1095 ns. A path that crosses a latch is therefore split into two checks, and the time moves from the first to the second one.

When the Borrow Is Too Large

The data can arrive too late for the latch. Replace the single delay cell by a chain of four slower delay cells, and the data arrives at 2.3721 ns, long after the latch has closed at 1.0 ns. The borrowing limit of this latch for that transition is 0.797 ns, and the check fails:

   0.0000    0.0000 ^ lat/GATE (sky130_fd_sc_hd__dlxtp_1)
   0.7970    0.7970   time borrowed from endpoint
             0.7970   data required time
            -2.3721   data arrival time
            -1.5751   slack (VIOLATED)

The required time is the maximum borrow, and the violation is the difference. In this case there is no help from the next stage. When the borrow is too much, the path has to be made faster, as for a normal setup violation, for example with a shorter chain of cells.

Hold at a Latch

The hold check of a latch is made at the closing edge. New data must not reach the latch before it has closed on the old data. In the example, the hold check uses the falling edge at 1.0 ns, with a hold time of 0.0353 ns, so that the required time is 0.9647 ns, and the data launched at the next edge (2.0 ns) arrives at 2.4780 ns. The hold slack is 1.5133 ns.

Why Use Latches

Latches use less area than flip-flops, and time borrowing evens out the delay between stages: a stage that is a little too slow can borrow from the next one, which is a little too fast. For this reason, designs that use latches deliberately, such as some processors, can reach higher speeds. The price is a more complicated analysis, and the risk that an unintended latch appears. A latch in RTL that was not meant to be there, from an incomplete if, is a common coding error.

Common Mistakes