Setup and Hold Checks

Setup and hold are the two fundamental timing checks. Every other check in STA is a variation of one of them. Think of a camera taking a photo: the subject must stand still for a moment before the shutter clicks and for a moment after it. A flip-flop is the camera, the clock edge is the click, and the data is the subject. The data must be stable in a small window around the clock edge. Setup is the part of the window before the edge, and hold is the part after it.

8 min read | Intermediate

What You'll Learn

• State the setup and hold requirement of a flip-flop
• Write and apply the setup and hold inequalities for a register-to-register path
• Explain why hold slack does not depend on the clock period
• Describe how clock uncertainty and process corners affect the two checks

The Flip-Flop Requirement

A flip-flop captures the value at its D pin on the active clock edge. To do so reliably, D must not change inside a window around that edge.

• The setup time is how long D must be stable before the clock edge.
• The hold time is how long D must stay stable after the clock edge.

Both values come from the library. In our run, the sky130 flip-flop has a setup time of 0.1174 ns, and a hold time of -0.0583 ns. A negative hold time just means the window ends slightly before the clock edge.

A setup check verifies the front of the window for every path that ends at a flip-flop, and a hold check verifies the back of it.

The Setup Check

Data launched by one clock edge must arrive and settle before the next capture edge, minus the setup time. The setup check runs from the launch edge to the closest following capture edge, so the clock period is part of it.

The diagram shows the clock twice. The launch clock is what the first flip-flop r1 sees, and the capture clock is what the second flip-flop r2 sees. It is the same clock, but they play different roles: the launch clock starts the data on its way, and the capture clock decides when the data is taken in. For setup, the capture edge that counts is the next one, one period after the launch edge.

Tlaunch + Tclk-to-Q + Tdp  <=  Tcapture + Tperiod - Tsetup

Here Tlaunch and Tcapture are the clock arrival times at the two flip-flops, and Tdp is the delay of the logic between them. This is the check that limits the speed of the design, and it always uses the longest, or max, path. For our path from r1 to r2 with ideal clocks, the left side is 0 + 0.2874 + 0.1450 = 0.4323 ns. The right side is 0 + 2.0 - 0.1174 = 1.8826 ns, and the difference is the slack.

             0.0000    2.0000    2.0000   clock clk (rise edge)
                       0.0000    2.0000   clock network delay (ideal)
                       0.0000    2.0000   clock reconvergence pessimism
                                 2.0000 ^ _6_/CLK (sky130_fd_sc_hd__dfxtp_1)
                      -0.1174    1.8826   library setup time
                                 1.8826   data required time
                                -0.4323   data arrival time
                                 1.4502   slack (MET)

The Hold Check

The hold check guards against data racing through. When a clock edge launches new data from the first flip-flop, the second flip-flop is capturing its own data on that same edge. In the diagram, the launch clock and the capture clock show the same edge at time 0, so the capture flop is still taking in the old data at the moment the new data starts its journey. The new data must not reach it too soon, or it overwrites the data it is supposed to capture.

Tlaunch + Tclk-to-Q + Tdp  >=  Tcapture + Thold

The hold check uses the same clock edge at both ends and the shortest, or min, path. In our design the earliest data reaches r2 after 0.3058 + 0.0599 = 0.3657 ns, and the requirement is -0.0583 ns, so the hold slack is 0.4241 ns.

                                 0.3657   data arrival time
             0.0000    0.0000    0.0000   clock clk (rise edge)
                       0.0000    0.0000   clock network delay (ideal)
                       0.0000    0.0000   clock reconvergence pessimism
                                 0.0000 ^ _6_/CLK (sky130_fd_sc_hd__dfxtp_1)
                      -0.0583   -0.0583   library hold time
                                -0.0583   data required time
                                 0.4241   slack (MET)

There is no clock period in the inequality. That is the key difference between the two checks.

Setup and Hold Side by Side

Slowing the clock cures setup violations, because it gives the data more time. It cannot cure a hold violation. The data race happens within one clock edge, whatever the period. The chart below shows the worst slack at the data pin of r2 as the period changes.

Margin and Corners

Real designs keep a safety margin on both checks. The constraint file (SDC) holds the margin as set_clock_uncertainty, which, with a single value, makes both the setup and the hold requirement harder by the same amount. Separate values for setup and hold can be given, and the hold value is usually smaller, because clock jitter does not matter for hold. A corner is a set of operating conditions, such as a hot chip with a low supply voltage, in which cells run slower or faster than usual. Corners work in opposite directions on the two checks. Cells are slowest at the slow corner and fastest at the fast corner, so setup is tightest at the slow corner and hold at the fast one. These are the worst setup and hold slacks of our design in the three sky130 corners, with a 2.0 ns period:

Setup slack shrinks toward the slow corner, hold slack shrinks toward the fast one. Sign-off therefore checks setup at the slow corner and hold at the fast one. A later chapter covers corners in depth.

Common Mistakes

set_clock_uncertainty 0.5 [get_clocks clk]